Advanced data converters

Advanced Data Converters

Volumn 9781107005570, Issue , 2011, Pages 1-239

  Manganaro, Gabriele ^a  

^a Analog Devices Inc UK   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMMERCE;

ARCHITECTURE SELECTION; BASIC PRINCIPLES; CONVERTER ARCHITECTURE; DATA CONVERTER; DESIGN TECHNIQUE; MATHEMATICAL PROOF; PERFORMANCE DATA; TIME TO DIGITAL CONVERTERS;

FREQUENCY CONVERTERS;

EID: 84926085532     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1017/CBO9780511794292     Document Type: Book

References (416)

1. S. Inouye, M. Robles-Bruce, and M. Scherer, "2009 data converters," Databeans Inc., Reno, NV, technical report, June 2009.
2. S. Inouye, M. Robles-Bruce, and M. Scherer, "2010 data converters," Databeans Inc., Reno, NV, technical report, June 2010.
3. K. Bult, "Embedded analog-to-digital converters," in European Solid-State Circuits Conference, 2009, pp. 52-64.
4. W. Kester, "Precision measurement and sensor conditioning," in The Data Conversion Handbook, W. Kester, Ed. Elsevier, Burlington, MA, 2005, pp. 539-561.
5. R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI: Design Techniques for Analog and Digital Circuits, Electronic Engineering Series. McGraw-Hill, New York, NY, 1990.
6. J. Márkus, J. Silva, and G. C. Temes, "Theory and applications of incremental ∑-Δ converters," IEEE Transactions on Circuits and Systems - Part I, vol. 51, no. 4, pp. 678-690, 2004.
7. W. Kester, "Digital audio," in The Data Conversion Handbook, W. Kester, Ed. Elsevier, Burlington, MA, 2005, pp. 591-605.
8. J. P. Conti, "Wake up to wireless," IET Engineering & Technology, vol. 5, no. 13, pp. 14-15, 2010.
9. A. Sheikholeslami, "ISSCC 2011 forum on high-speed transceivers: Standards, challenges, and future," in International Solid-State Circuits Conference, IEEE, 2011.
10. W. Kester, "Software radio and IF sampling," in The Data Conversion Handbook, W. Kester, Ed. Elsevier, Burlington, MA, 2005, pp. 633-666.
11. V. K. Garg and J. E. Wilkes, Wireless and Personal Communication Systems. Prentice Hall, New York, NY, 1996.
12. P. Hendriks, "Specifying communications DAC's," IEEE Spectrum, vol. 34, no. 7, pp. 58-69, 1997.
13. C. Edwards, "In the balance," IET Engineering & Technology, vol. 5, no. 14, pp. 60-62, 2010.
14. G. Manganaro and D. Leenaerts, "ISSCC 2011 forum on advanced transmitters for wireless infrastructure," in International Solid-State Circuits Conference, IEEE, 2011.
15. A. A. Abidi, "The path to the software-defined radio receiver," IEEE International Journal of Solid State Circuits, vol. 42, no. 5, pp. 954-966, 2007.
16. P. B. Kenington and L. Astier, "Power consumption of A/D converters for software radio applications," IEEE Transactions on Vehicular Technology, vol. 49, no. 2, pp. 643-650, 2000.
17. J. Sevenhans and Z.-Y. Chang, "A/D and D/A conversion for telecommunication," IEEE Circuits & Devices Magazine, vol. 14, no. 1, pp. 32-42, 1998.
18. L. Breems and J. H. Huijsing, Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers. Kluwer, Dordrecht, the Netherlands, 2001.
19. EE Times editors, "Medical electronics gets personal," http://www.nxtbook.com/nxtbooks/cmp/eetimes\medelec\ 20101108/\#/3/OnePage, 2010.
20. C. Hammerschmidt, "National Semi to commercialize sigma delta ADC," http://www. eetimes.com/electronics-news/4190836/National-Semi-to-commercialize-Sigma-Delta- ADC, 2008.
21. C. Stagni, C. Guiducci, L. Benini et al., "CMOS DNA sensor array with integrated A/D conversion based on label-free capacitance measurement," IEEE International Journal of Solid State Circuits, vol. 31, no. 12, pp. 2956-2964, 2006.
22. A. C.-W. Wong, D. McDonagh, G. Kathiresan et al., "A 1 V, micropower system-on-chip for vital-sign monitoring in wireless body sensor networks," in International Solid-State Circuits Conference, 2008, pp. 138-139.
23. S. Chou, "Integration and innovation in the nanoelectronics era," in International Solid-State Circuits Conference, 2005, pp. 36-41.
24. T.-C. Chen, "Where CMOS is going: Trendy hype vs. real technology," in International Solid-State Circuits Conference, 2006, pp. 22-28.
25. G. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, pp. 114-117, 1965.
26. G. Moore, "No exponential is forever: But 'forever' can be delayed!," in International Solid-State Circuits Conference, 2003, pp. 20-23.
27. C. Edwards, "Analogue circuits squeeze chip design," IET Engineering & Technology, vol. 5, no. 8, pp. 14-15, 2010.
28. Y. Chiu, B. Nikolić, and P. R. Gray, "Scaling of analog-to-digital converters into ultra-deepsubmicron CMOS," in Custom Integrated Circuits Conference, 2005, pp. 375-382.
29. K. Bult, "The effect of technology scaling on power dissipation in analog circuits," in Analog Circuit Design, M. Steyaert, A. H. van Roermund, and J. H. Huijsing, Eds. Springer-Verlag, Berlin, Germany, 2006, pp. 251-290.
30. K. Bult, "Analog design in deep sub-micron CMOS," in European Solid-State Circuits Conference, 2000, pp. 126-132.
31. B. Murmann, P. Nikaeen, D. J. Connelly, and R. W. Dutton, "Impact of scaling on analog performance and associated modeling needs," IEEE Transactions on Electron Devices, vol. 53, no. 9, pp. 2160-2167, 2006.
32. M. Boulemnakher, E. Andre, J. Roux, and F. Paillardet, "A 1.2V 4.5mW 10 b 100 MS/s pipeline ADC in a 65 nm CMOS," in International Solid-State Circuits Conference, 2008, pp. 250-251.
33. D. Johns and K. Martin, Analog Integrated Circuit Design. John Wiley & Sons, New York, NY, 1997.
34. F. Maloberti, Data Converters. Springer-Verlag, Berlin, Germany, 2009.
35. A. Thomsen, D. Kasha, and W. Lee, "A five stage chopper stabilized instrumentation amplifier using feedforward compensation," in VLSI Circuits Conference, 1998, pp. 220- 223.
36. J. Yan and R. L. Geiger, "Fast-settling amplifier design using feedforward compensation technique," in IEEE Midwest Symposium on Circuits and Systems, 2000, pp. 494-498.
37. M. Moyal, M. Groepl, H. Werker, G. Mitteregger, and J. Schambacher, "A 700/900 mW/channel CMOS dual analog front-end IC for VDSL with integrated 11.5/14.5 dBm line drivers," in International Solid-State Circuits Conference, 2003, pp. 416-417.
38. J. Harrison and N. Weste, "A 500MHz CMOS anti-aliasing filter using feed-forward opamps with local common-mode feedback," in International Solid-State Circuits Conference, 2003, pp. 132-133.
39. B. K. Thandri and J. Silva-Martínez, "A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors," IEEE International Journal of Solid State Circuits, vol. 38, no. 2, pp. 237-243, 2003.
40. R. Ito and T. Itakura, "Phase compensation techniques for low-power operational amplifiers," IEICE Transactions on Electronics, vol. 93-C, no. 6, pp. 730-740, 2010.
41. A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE International Journal of Solid State Circuits, vol. 34, no. 5, pp. 599-606, 1999.
42. M. J. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE International Journal of Solid State Circuits, vol. 24, no. 5, pp. 1433- 1440, 1989.
43. P. R. Kinget, "Device mismatch and tradeoffs in the design of analog circuits," IEEE International Journal of Solid State Circuits, vol. 40, no. 6, pp. 1212-1224, 2005.
44. P. G. Drennan and C. C. McAndrew, "Understanding MOSFET mismatch for analog design," IEEE International Journal of Solid State Circuits, vol. 38, no. 3, pp. 450-456, 2003.
45. B. P.Wong, F. Zach, V.Moroz et al., Eds., Nano-CMOS Design for Manufacturability. John Wiley & Sons, New York, NJ, 2009.
46. L.-T. Pang and B. Nikolić, "Measurements and analysis of process variability in 90 nm CMOS," IEEE International Journal of Solid State Circuits, vol. 44, no. 5, pp. 1655-1663, 2009.
47. J. Hurwitz, "ISSCC 2011 tutorial on layout: The other half of nanometer analog design," in International Solid-State Circuits Conference, IEEE, 2011.
48. A. M. A. Ali, A. Morgan, C. Dillon et al., "A 16 b 250 MS/s IF-sampling pipelined A/D converter with background calibration," IEEE International Journal of Solid State Circuits, vol. 45, no. 12, pp. 2602-2612, 2010.
49. R. Payne, M. Corsi, D. Smith, S. Kaylor, and D. Hsieh, "A 16 b 100-to-160 MS/s Si Ge BiCMOS pipelined ADC with 100 dBFS SFDR," in International Solid-State Circuits Conference, 2010, pp. 294-295.
50. D. Robertson and T. Montalvo, "Issues and trends in RF and mixed signal integration and partitioning," IEEE Communications Magazine, vol. 46, no. 9, pp. 52-56, 2008.
51. D. Robertson and M. Kessler, "Smart partitioning," in The Data Conversion Handbook, W. Kester, Ed. Elsevier, Burlington, MA, 2005, pp. 273-280.
52. B. Razavi, Principles of Data Conversion System Design. IEEE Press, Piscataway, NJ, 1995.
53. R. J. van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd edn. Kluwer, Dordrecht, the Netherlands, 2003.
54. B. Murmann, EE315: VLSI Data Conversion Circuits - Class Notes. Stanford University, Stanford, CA, 2008.
55. W. Kester, "The importance of data converter static specifications - don't lose sight of the basics!," Analog Devices, Tutorial MT-010, 2009.
56. Maxim Staff, "INL/DNL measurements for high-speed analog-to-digital converters (ADCs)," Maxim Integrated Products, Application Note 283, 2001.
57. P. M. Figueiredo and J. C. Vital, Offset reduction techniques in high-speed analog-to-digital converters. Springer-Verlag, Berlin, Germany, 2009.
58. B. Brannon, "Overcoming converter nonlinearities with dither," Analog Devices, Application Note AN-410, 1995.
59. W. Kester and J. Bryant, "Data converter AC errors," in The Data Conversion Handbook, W. Kester, Ed. Elsevier, Burlington, MA, 2005, pp. 83-122.
60. W. Kester, Ed., The Data Conversion Handbook. Elsevier, Burlington, MA, 2005.
61. L. A. Singer and T. L. Brooks, "A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter," in VLSI Circuits Conference, 1996, pp. 94-95.
62. J. Li, R. LeBoeuf, M. Courcy, and G. Manganaro, "A 1.8V 10b 210MS/s CMOS pipelined ADC featuring 86dB SFDRwithout calibration," in Custom Integrated Circuits Conference, 2007, pp. 317-320.
63. D. A. Mercer, "Low-power approaches to high-speed current-steering digital-to-analog converters in 0.18-μm CMOS," IEEE International Journal of Solid State Circuits, vol. 42, no. 8, pp. 1688-1698, 2007.
64. A. Hastings, The Art of Analog Layout, 2nd edn. Prentice Hall, New York, NY, 2005.
65. C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization," Proceedings of the IEEE, vol. 84, no. 11, pp. 1584-1614, 1996.
66. J. Yang and H.-S. Lee, "A CMOS 12-bit 4 MHz pipelined A/D converter with commutative feedback capacitor," in Custom Integrated Circuits Conference, 1996, pp. 427- 430.
67. I. Galton and P. Carbone, "A rigorous error analysis of D/A conversion with dynamic element matching," IEEE Transactions on Circuits and Systems - Part II, vol. 42, no. 12, pp. 763-772, 1995.
68. I. Galton, "Why dynamic-element-matching DACs work," IEEE Transactions on Circuits and Systems - Part II, vol. 57, no. 2, pp. 69-74, 2010.
69. S. Devarajan, L. Singer, D. Kelly et al., "A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS pipeline ADC," IEEE International Journal of Solid State Circuits, vol. 44, no. 12, pp. 3305-3313, 2009.
70. B. Grob and C. Herndon, Basic Television and Video Systems, 6th edn. McGraw-Hill, New York, NY, 1998.
71. I. A. Chaudhry, S.-U. Kwak, G. Manganaro, M. Sarraj, and T. L. Viswanathan, "A triple 8 b, 80MSPS, 3.3V graphics digitizer," in IEEE International Symposium on Circuits and Systems, vol. 5, 2000, pp. 557-560.
72. J. Li, G. Manganaro, M. Courcy, B.-M. Min, L. Tomasi, A. Alam, and R. Taylor, "A 10b 170 MS/s CMOS pipelined ADC featuring 84dB SFDR without calibration," in VLSI Circuits Conference, 2006, pp. 226-227.
73. R. C. Taft, C. A. Menkus, M. R. Tursi, O. Hidri, and V. Pons, "A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency," IEEE International Journal of Solid State Circuits, vol. 39, no. 12, pp. 2107-2115, 2004.
74. M. Gustavsson, J. J. Wikner, and N. N. Tan, CMOS Data Converters for Communications. Kluwer, Dordrecht, the Netherlands, 2000.
75. B. Metzler, Audio Measurement Handbook, 1st edn. Audio Precision, Inc., Beaverton, OR, 1993.
76. C. Motschenbacher and J. Connelly, Low Noise Electronic System Design. John Wiley & Sons, New York, NY, 1993.
77. J. Munson, "Understanding high-speed DAC testing and evaluation," Analog Devices, Application Note AN-928, 2008.
78. P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated Circuits. Kluwer, Dordrecht, the Netherlands, 1998.
79. B. Brannon, "Sampled systems and the effects of clock phase noise and jitter," Analog Devices, Application Note AN-756, 2004.
80. R. H.Walden, "Analog-to-digital converter survey and analysis," IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, pp. 539-550, 1999.
81. R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. John Wiley & Sons, New York, NY, 2005.
82. B. Murmann, "A/D converter trends: Power dissipation, scaling and digitally assisted architectures," in Custom Integrated Circuits Conference, 2008, pp. 105-112.
83. H.-S. Lee and C. G. Sodini, "Analog-to-digital converters digitizing the analog world," Proceedings of the IEEE, vol. 96, no. 2, pp. 323-334, 2008.
84. B. E. Jonsson, "A survey of A/D-converter performance evolution," in IEEE International Conference on Electronics, Circuits, and Systems, 2010, pp. 768-771.
85. B. Murmann, "ADC performance survey 1997-2011," http://www.stanford.edu/∼murmann/adcsurvey.html, 2011.
86. P. Palmers and M. S. J. Steyaert, "A 10-bit, 1.6 GS/s 27-mW current-steering D/A converter with 550-MHz 54-dB SFDR bandwidth in 130-nm CMOS," IEEE Transactions on Circuits and Systems - Part I, no. 11, pp. 2870-2879, 2010.
87. A. Van den Bosch, M. S. J. Steyaert, and W. Sansen, "Solving static and dynamic performance limitations for high-speed D/A converters," in Analog Circuit Design: Scalable Analog Circuit Design, High-Speed D/A Converters, RF Power Amplifiers, J. H. Huijsing, M. Steyaert, and A. van Roermund, Eds. Kluwer, Dordrecht, the Netherlands, 2002, pp. 189-210.
88. D. Giotta, P. Pessl, M. Clara, W. Klatzer, and R. Gaggl, "Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13 μm CMOS," in European Solid-State Circuits Conference, 2004, pp. 163-166.
89. M. Clara, W. Klatzer, B. Seger, A. Di Giandomenico, and L. Gori, "A 1.5V 200 MS/s 13 b 25mW DAC with randomized nested background calibration in 0.13 μm CMOS," in International Solid-State Circuits Conference, 2007, pp. 250-251.
90. C.-H. Lin, F.M. L. van derGoes, J.R.Westra et al., "A12 bit 2.9 GS/s DAC with IM3< −60 dBc beyond 1 GHz in 65 nm CMOS," IEEE International Journal of Solid State Circuits, vol. 44, no. 12, pp. 3285-3293, 2009.
91. R. Reeder, W. Green, and R. Shillito, "Analog-to-digital converter clock optimization: A test engineering perspective," Analog Dialogue, vol. 42, no. 2, pp. 1-7, 2008.
92. P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th edn. John Wiley & Sons, New York, NY, 2001.
93. A. P. Brokaw, "A temperature sensor with single resistor set-point programming," IEEE International Journal of Solid State Circuits, vol. 31, no. 12, pp. 1908-1915, 1996.
94. P. R. Holloway and J. Wan, "Emitter area trim scheme for a PTAT current source," US Patent 7 443 226, 2007.
95. P. R. Holloway and J.Wan, "Self-regulating process-error trimmable PTAT current source," US Patent 7 236 048, 2007.
96. G. Ge, C. Zhang, G. Hoogzaad, and K. Makinwa, "A single-trim CMOS bandgap reference with a 3σ inaccuracy of ±0.15% from −40°C to 125°C," in International Solid-State Circuits Conference, 2010, pp. 78-79.
97. P. Baginski, P. Brokaw, and S. Wurcer, "A complete 18-bit audio D/A converter," in International Solid-State Circuits Conference, 1990, pp. 202-203.
98. U.-K. Moon and B.-S. Song, "Background digital calibration techniques for pipelined ADC's," IEEE Transactions on Circuits and Systems - Part II, vol. 44, no. 2, pp. 102-109, 1997.
99. S.-U. Kwak, B.-S. Song, and K. L. Bacrania, "A 15-b, 5-Msample/s low-spurious CMOS ADC," IEEE International Journal of Solid State Circuits, vol. 32, no. 12, pp. 1866-1875, 1997.
100. H.-S. Lee, D. A. Hodges, and P. R. Gray, "A self-calibrating 15 bit CMOS A/D converter," IEEE International Journal of Solid State Circuits, vol. 19, no. 6, pp. 813-819, 1984.
101. A. Karanicolas, H.-S. Lee, and K. L. Bacrania, "A 15-b 1-Msample/s digitally selfcalibrated pipeline ADC," IEEE International Journal of Solid State Circuits, vol. 28, no. 12, pp. 1207-1215, 1993.
102. J. R. Raol, G.Girjia, and J. Singh, Modelling and Parameter Estimation of Dynamic Systems. IEE Control Engineering. Institution of Engineering and Technology (IET) London, 2004.
103. B. C. Levy, Principles of Signal Detection and Parameter Estimation. Springer-Verlag, Berlin, Germany, 2009.
104. A. van den Bos, Parameter Estimation for Scientists and Engineers. John Wiley & Sons, New York, NY, 2007.
105. R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing. John Wiley & Sons, New York, NY, 1986.
106. B. Murmann and V. Gopinathan, "ISSCC 2011 evening session on data converter breakthrough in retrospect," in International Solid-State Circuits Conference, IEEE, 2011.
107. R. J. van de Plassche and R. E. J. van der Grift, "A high-speed 7 bit A/D converter," IEEE International Journal of Solid State Circuits, vol. 14, no. 6, pp. 938-943, 1979.
108. 2," IEEE International Journal of Solid State Circuits, vol. 32, no. 12, pp. 1887-1895, 1997.
109. K. Kattmann and J. Barrow, "A technique for reducing differential non-linearity errors in flash A/D converters," in International Solid-State Circuits Conference, 1991, pp. 170-171.
110. H. Pan and A. A. Abidi, "Spatial filtering in flash A/D converters," IEEE Transactions on Circuits and Systems - Part II, vol. 50, no. 8, pp. 424-436, 2003.
111. K. Nagaraj, D. A. Martin, M. Wolfe et al., "A dual-mode 700-Msamples/s 6-bit 200- Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process," IEEE International Journal of Solid State Circuits, vol. 35, no. 12, pp. 1760-1768, 2000.
112. M. Choi and A. A. Abidi, "A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS," IEEE International Journal of Solid State Circuits, vol. 36, no. 12, pp. 1847-1858, 2001.
113. P. C. S. Scholtens and M. Vertregt, "A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination," IEEE International Journal of Solid State Circuits, vol. 37, no. 12, pp. 1599-1609, 2002.
114. Y.-I. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, "A 10 b 100 MSample/s CMOS pipelined ADC with 1.8V power supply," in International Solid-State Circuits Conference, 2001, pp. 580-583.
115. K. Poulton, R. Neff, A. Muto et al., "A 4 GSample/s 8 b ADC in 0.35 μm CMOS," in International Solid-State Circuits Conference, 2002, pp. 166-167.
116. K. Poulton, R. Neff, B. Setterberg et al., "A 20GS/s 8 b ADC with a 1MB memory in 0.18 μm CMOS," in International Solid-State Circuits Conference, 2003, pp. 318-319.
117. G. Manganaro, "Feed-forward approach for timing skew in interleaved and double-sampled circuits," IEE Electronics Letters, vol. 37, no. 9, pp. 552-553, 2001.
118. Y. Li and E. Sánchez-Sinencio, "A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC," IEEE International Journal of Solid State Circuits, vol. 38, no. 8, pp. 1405-1410, 2003.
119. G. Geelen and E. Paulus, "An 8 b 600 MS/s 200mW CMOS folding A/D converter using an amplifier preset technique," in International Solid-State Circuits Conference, 2004, pp. 254-255.
120. R. C. Taft, C. A. Menkus, M. R. Tursi, O. Hidri, and V. Pons, "Advances in high-speed ADC architectures using offset calibration," in Analog Circuit Design: High-Speed AD Converters, Automotive Electronics and Ultra-Low Power Wireless, A. H. M. van Roermund, H. Casier, and M. Steyaert, Eds. Kluwer, Dordrecht, the Netherlands, 2006, pp. 189-210.
121. P. Vorenkamp and R. Roovers, "A 12-b, 60-MSample/s cascaded folding and interpolating ADC," IEEE International Journal of Solid State Circuits, vol. 32, no. 12, pp. 1876-1886, 1997.
122. M.-J. Choe, B.-S. Song, and K. Bacrania, "An 8-b 100-MSample/s CMOS pipelined folding ADC," IEEE International Journal of Solid State Circuits, vol. 36, no. 2, pp. 184-194, 2001.
123. Y. Nakajima, A. Sakaguchi, T. Ohkido, T. Matsumoto, and M. Yotsuyanagi, "A selfbackground calibrated 6 b 2.7 GS/s ADC with cascade-calibrated folding-interpolating architecture," in VLSI Circuits Conference, 2007, pp. 266-267.
124. Y. Nakajima, A. Sakaguchi, T. Ohkido, T. Matsumoto, and M. Yotsuyanagi, "A background self-calibrated 6 b 2.7 GS/s ADC with cascade-calibrated folding-interpolating architecture," IEEE International Journal of Solid State Circuits, vol. 45, no. 4, pp. 707-718, 2010.
125. I. Bogue and M. P. Flynn, "A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS," in Custom Integrated Circuits Conference, 2007, pp. 337-340.
126. K. Makigawa, K. Ono, T. Ohkawa, K.Matsuura, and M. Segami, "A 7 bit 800 Msps 120mW folding and interpolation ADC using a mixed-averaging scheme," in VLSI Circuits Conference, 2006, pp. 138-139.
127. A. Razzaghi, S.-W. Tam, P. Kalkhoran et al., "A single-channel 10 b 1GS/s ADC with 1- cycle latency using pipelined cascaded folding," in Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2008, pp. 265-266.
128. Y. Chen, Q. Huang, and T. Burger, "A 1.2V 200-MS/s 10-bit folding and interpolating ADC in 0.13-μm CMOS," in European Solid-State Circuits Conference, 2007, pp. 155-158.
129. R. C. Taft, P. A. Francese, M. R. Tursi et al., "A 1.8 V 1.0 GS/s 10 b self-calibrating unifiedfolding- interpolating ADC with 9.1 ENOB at Nyquist frequency," IEEE International Journal of Solid State Circuits, vol. 44, no. 12, pp. 3294-3304, 2009.
130. G. Van der Plas, S. Decoutere, and S. Donnay, "A 0.16 pJ/conversion-step 2.5mW1.25 GS/s 4 b ADC in a 90 nm digital CMOS process," in International Solid-State Circuits Conference, 2006, pp. 566-567.
131. N. Sayiner, H. Sorensen, and T. Viswanathan, "A new signal acquisition technique," in IEEE International Symposium on Circuits and Systems, 1992, pp. 1140-1143.
132. N. Sayiner, H. Sorensen, and T. Viswanathan, "A level-crossing sampling scheme for A/D conversion," IEEE Transactions on Circuits and Systems - Part II, vol. 43, no. 4, pp. 335-339, 1996.
133. Y. Tsividis, "Event-driven data acquisition and digital signal processing - a tutorial," IEEE Transactions on Circuits and Systems - Part II, vol. 57, no. 8, pp. 577-581, 2010.
134. Y. Tsividis, "Event-driven data acquisition and continuous-time digital signal processing," in Custom Integrated Circuits Conference, 2010, pp. 1-8.
135. Y. Tsividis, "Event-driven, continuous-time ADCs and DSPs for adapting power dissipation to signal activity," in IEEE International Symposium on Circuits and Systems, 2010, pp. 3581-3584.
136. C. S. Burrus, R.A.Gopinath, and H. Guo, Introduction to Wavelets and Wavelet Transforms: A Primer. Prentice Hall, New York, NY, 1998.
137. G. Russell, D. J. Kinniment, E. G. Chester, and M. R. McLauchlan, CAD for VLSI. Van Nostrand Reinhold, London, UK, 1985.
138. J. K. White and A. Sangiovanni-Vincentelli, Relaxation Techniques for the Simulation of VLSI Circuits. Kluwer, Dordrecht, the Netherlands, 1987.
139. P. H. Ellis, "Extension of phase plane analysis to quantized systems," IRE Transactions on Automatic Control, vol. 4, no. 2, pp. 43-54, 1959.
140. R. C. Dorf, M. C. Farren, and C. A. Phillips, "Adaptive sampling frequency for sampleddata control systems," IRE Transactions on Automatic Control, vol. 7, no. 1, pp. 38-47, 1962.
141. D. Donoho, "Compressed sensing," IEEE Transactions on Information Theory, vol. 52, no. 4, pp. 1289-1306, 2006.
142. M. Trakimas and S. R. Sonkusale, "An adaptive resolution asynchronous ADC architecture for data compression in energy constrained sensing applications," IEEE Transactions on Circuits and Systems - Part I, vol. 58, 2011.
143. F. Akopyan, R. Manohar, and A. B. Apsel, "A level-crossing flash asynchronous analog-todigital converter," in IEEE International Symposium on Asynchronous Circuits and Systems, 2006, pp. 12-22.
144. B. Schell and Y. Tsividis, "A continuous-time ADC/DSP/DAC system with no clock and with activity-dependent power dissipation," IEEE International Journal of Solid State Circuits, vol. 43, no. 11, pp. 2472-2481, 2008.
145. M. Trakimas and S. R. Sonkusale, "A 0.8 V asynchronous ADC for energy constrained sensing applications," in Custom Integrated Circuits Conference, 2008, pp. 173-176.
146. M. Kurchuk and Y. Tsividis, "Signal-dependent variable-resolution clockless A/D conversion with application to continuous-time digital signal processing," IEEE Transactions on Circuits and Systems - Part I, vol. 57, no. 5, pp. 982-991, 2010.
147. J. C. Schelleng, "Code modulation communication system," US Patent 2 453 461, 1948.
148. B. M. Gordon and E. T. Colton, "Signal conversion apparatus," US Patent 2 997 704, 1961.
149. A. Baschirotto, "ISSCC 2009 tutorial succesive approximation register (SAR) A/D converters," in International Solid-State Circuits Conference, IEEE, 2009.
150. J. L. McCreary and P. R. Gray, "All-MOS charge redistribution analog-to-digital conversion techniques, part I," IEEE International Journal of Solid State Circuits, vol. 10, no. 6, pp. 371-379, 1975.
151. F. Kuttner, "A 1.2V 10 b 20 MSample/s non-binary successive approximation ADC in 0.13 μm CMOS," in International Solid-State Circuits Conference, 2002, pp. 136-137.
152. P. Confalonieri, M. Zamprogno, F. Girardi, G. Nicollini, and A. Nagari, "A 2.7mW lMSPS 10 b analog-to-digital converter with built-in reference buffer and l LSB accuracy programmable input ranges," in European Solid-State Circuits Conference, 2004, pp. 255-258.
153. J. Craninckx and G. Van der Plas, "A 65 fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9 b charge-sharing SAR ADC in 90 nm digital CMOS," in International Solid-State Circuits Conference, 2007, pp. 246-247.
154. G. Manganaro, S.-U. Kwak, and A. Bugeja, "A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer," IEEE International Journal of Solid State Circuits, vol. 39, no. 11, pp. 1829-1838, 2004.
155. S. H. Lewis, H. S. Fetterman, G. F. Gross Jr., R. Ramachandran, and T. R. Viswanathan, "A 10-b 20-Msample/s analog-to-digital converter," IEEE International Journal of Solid State Circuits, vol. 27, no. 3, pp. 351-358, 1992.
156. V. Giannini, P. Nuzzo, V. Chironi et al., "An 820 μW 9 b 40MS/s noise-tolerant dynamic- SAR ADC in 90 nm digital CMOS," in International Solid-State Circuits Conference, 2008, pp. 238-239.
157. S.-W. M. Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS," IEEE International Journal of Solid State Circuits, vol. 41, no. 12, pp. 2669-2680, 2006.
158. B. P. Ginsburg and A. P. Chandrakasan, "An energy-efficient charge recycling approach for a SAR converter with capacitive DAC," in IEEE International Symposium on Circuits and Systems, vol. 1, 2005, pp. 184-187.
159. B. P. Ginsburg and A. P. Chandrakasan, "500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC," IEEE International Journal of Solid State Circuits, vol. 42, no. 4, pp. 739-747, 2007.
160. M. van Elzakker, E. van Tuijl, P. Geraedts et al., "A 10-bit charge-redistribution ADC consuming 1.9 μW at 1 MS/s," IEEE International Journal of Solid State Circuits, vol. 45, no. 5, pp. 1007-1015, 2010.
161. 2," in IEEE Symposium on Low Power Electronics, 1994, pp. 100-101.
162. D. Draxelmayr, "A 6 b 600MHz 10mW ADC array in digital 90 nm CMOS," in International Solid-State Circuits Conference, 2004, pp. 264-265.
163. B. P. Ginsburg and A. P. Chandrakasan, "Highly interleaved 5-bit, 250-MSample/s, 1.2-mW ADC with redundant channels in 65-nm CMOS," IEEE International Journal of Solid State Circuits, vol. 43, no. 12, pp. 2641-2650, 2008.
164. J. McNeill, M. C. W. Coln, and B. J. Larivee, " 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC," IEEE International Journal of Solid State Circuits, vol. 40, no. 12, pp. 2437-2445, 2005.
165. G. Van der Plas and B. Verbruggen, "A 150 MS/s 133 μW 7 bit ADC in 90 nm digital CMOS," IEEE International Journal of Solid State Circuits, vol. 43, no. 12, pp. 2631-2640, 2008.
166. C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, "An 18 b 12.5 MS/s ADC with 93 dB SNR," IEEE International Journal of Solid State Circuits, vol. 45, no. 12, pp. 2647-2654, 2010.
167. 2 8 b 400 MS/s SAR ADC with 2 b/cycle and resistive DAC in 65 nm CMOS," in International Solid-State Circuits Conference, 2011, pp. 187-188.
168. E. M. Deloraine, S. Van Mierlo, and B. Derjavitch, "Méthode et système de transmission par impulsions," French Patent 932 140, 1946.
169. E. M. Deloraine, S. Van Mierlo, and B. Derjavitch, "Communication system utilizing constant amplitude pulses of opposite polarities," US Patent 2 629 857, 1953.
170. F. de Jager, "Delta modulation: A method of PCM transmission using the one unit code," Phillips Research Report, vol. 7, pp. 542-546, 1952.
171. H. Van de Weg, "Quantizing noise of a single integration delta modulation system with an N-digit code," Phillips Research Report, vol. 8, pp. 367-385, 1953.
172. C. C. Cutler, "Differential quantization of communication signals," US Patent 2 605 361, 1952.
173. C. C. Cutler, "Transmission systems employing quantization," US Patent 2 927 962, 1960.
174. H. Inose, Y. Yasuda, and J. Murakami, "A telemetering system by code modulation - ∑-Δ modulation," IRE Transactions on Space Electronics and Telemetry, vol. 8, no. 9, pp. 204-209, 1962.
175. S. R. Norsworthy, R. Schreier, and G. C. Temes, Eds., Delta-Sigma Data Converters: Theory, Design and Simulation. IEEE Press, Piscataway, NJ, 1996.
176. S. Pavan, "Alias rejection of continuous-time Δ∑ modulators with switched-capacitor feedback DACs," IEEE Transactions on Circuits and Systems - Part I, vol. 58, no. 2, pp. 233-243, 2011.
177. M. Bolatkale, L. J. Breems, R. Rutten, and K. A. Makinwa, "A 4 GHz CT ADC with 70 dB DR and 74 dBFS THD in 125MHz BW," in International Solid-State Circuits Conference, 2011, pp. 470-471.
178. G. Mitteregger, C. Ebner, S. Mechnig et al., "A 20-mW 640-MHz CMOS continuous-time Δ∑ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB," IEEE International Journal of Solid State Circuits, vol. 41, no. 12, pp. 2641-2649, 2006.
179. R. H. van Veldhoven, R. Rutten, and L. J.Breems, "An inverter-based hybridΔ∑ modulator," in International Solid-State Circuits Conference, 2008, pp. 492-493.
180. S. Patón, A. Di Giandomenico, L. Hernández et al., "A 70-mW 300-MHz CMOS continuous-timeΔ∑ ADC with 15-MHz bandwidth and 11 bits of resolution," IEEE International Journal of Solid State Circuits, vol. 39, no. 7, pp. 1056-1063, 2004.
181. M.Keller, A. Buhmann, J. Sauerbrey, M. Ortmanns, and Y. Manoli, "Acomparative study on excess-loop-delay compensation techniques for continuous-time sigma-delta modulators," IEEE Transactions on Circuits and Systems - Part I, vol. 55, no. 11, pp. 3480-3487, 2008.
182. K. Nguyen, R. Adams, K. Sweetland, and H. Chen, "A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio," IEEE International Journal of Solid State Circuits, vol. 40, no. 12, pp. 2408-2415, 2005.
183. P. Morrow, M. Chamarro, C. Lyden et al., "A 0.18 μm 102 dB-SNR mixed CT SC audioband ADC," in International Solid-State Circuits Conference, 2005, pp. 178-179.
184. L. Dörrer, F. Kuttner, A. Santner et al., "A 2.2 mW, continuous-time Sigma-Delta ADC for voice coding with 95 dB dynamic range in a 65 nm CMO Sprocess," in European Solid-State Circuits Conference, 2006, pp. 195-198.
185. L. Dörrer, F. Kuttner, A. Santner et al., "A continuous time Δ∑ ADC for voice coding with 92 dB DR in 45 nm CMOS," in International Solid-State Circuits Conference, 2008, pp. 502-503.
186. I. Galton, "Delta-sigma data conversion in wireless transceivers," IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 1, pp. 303-315, 2002.
187. G. Raghavan, J. F. Jensen, J. Laskowski et al., "Architecture, design, and test of continuoustime tunable intermediate-frequency bandpass delta-sigma modulators," IEEE International Journal of Solid State Circuits, vol. 36, no. 1, pp. 5-13, 2001.
188. R. Schreier, J. Lloyd, L. Singer et al., "A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-333-kHz bandwidth," IEEE International Journal of Solid State Circuits, vol. 37, no. 12, pp. 1636-1644, 2002.
189. R. Schreier, N. Abaskharoun, H. Shibata et al., "A 375-mW quadrature bandpass Δ∑ ADC with 8.5-MHz BW and 90-dB DR at 44 MHz," IEEE International Journal of Solid State Circuits, vol. 41, no. 12, pp. 2632-2640, 2006.
190. L. J. Breems, R. Rutten, R. H. M. van Veldhoven, and G. van der Weide, "A 56 mW continuous-time quadrature cascaded Δ∑ modulator with 77 dB DR in a near zero- IF 20 MHz band," IEEE International Journal of Solid State Circuits, vol. 42, no. 12, pp. 2696-2705, 2007.
191. P. G. R. Silva, L. J. Breems, K. A. A. Makinwa, M. Raf Roovers, and J. H. Huijsing, "An IF-to-baseband Δ∑ modulator for AM/FM/IBOC radio receivers with a 118 dB dynamic range," IEEE International Journal of Solid State Circuits, vol. 42, no. 5, pp. 1076-1089, 2007.
192. B. K. Thandri and J. Silva-Martinez, "A 63 dB SNR, 75-mW bandpass RF Δ∑ ADC at 950 MHz using 3.8-GHz clock in 0.25-μm SiGe BiCMOS technology," IEEE International Journal of Solid State Circuits, vol. 42, no. 2, pp. 269-279, 2007.
193. W. Yang, W. Schofield, H. Shibata et al., "A 100mW 10 MHz-BW CT modulator with 87 dB DR and 91 dBc IMD," in International Solid-State Circuits Conference, 2008, pp. 498-499.
194. L. R. Carley, "A noise-shaping coder topology for 15+bit converters," IEEE International Journal of Solid State Circuits, vol. 24, no. 2, pp. 267-273, 1989.
195. R. T. Baird and T. S. Fiez, "Linearity enhancement of multibit Δ∑ A/D and D/A converters using data weighted averaging," IEEE Transactions on Circuits and Systems - Part II, vol. 42, no. 12, pp. 753-762, 1995.
196. R. E. Radke, A. Eshraghi, and T. S. Fiez, "A 14-bit current-mode Δ∑ DAC based upon rotated dataweighted averaging," IEEE International Journal of Solid State Circuits, vol. 35, no. 8, pp. 1074-1084, 2000.
197. F. Chen and B. H. Leung, "A high resolution multibit sigma-delta modulator with individual level averaging," IEEE International Journal of Solid State Circuits, vol. 30, no. 4, pp. 453- 460, 1995.
198. A. A. Hamoui and K. W. Martin, "High-order multibit modulators and pseudo dataweighted- averaging in low-oversampling Δ∑ ADCs for broad-band applications," IEEE Transactions on Circuits and Systems - Part I, vol. 51, no. 1, pp. 72-85, 2004.
199. N rotated walk switching scheme," IEEE Transactions on Circuits and Systems - Part II, vol. 53, no. 11, pp. 1264-1268, 2006.
200. 2 CT Δ∑ ADC with −97.7 dBc THD and 80 dB DR using low-latency DEM," in International Solid-State Circuits Conference, 2009, pp. 172-173.
201. J. Ryckaert, J. Borremans, B. Verbruggen et al., "A 2.4 GHz low-power sixth-order RF bandpass Δ∑ converter in CMOS," IEEE International Journal of Solid State Circuits, vol. 44, no. 11, pp. 2873-2880, 2009.
202. I. Galdi, E. Bonizzoni, P. Malcovati, G. Manganaro, and F. Maloberti, "40 MHz IF 1 MHz bandwidth two-path bandpass Δ∑ modulator with 72 dB DR consuming 16 mW," IEEE International Journal of Solid State Circuits, vol. 43, no. 7, pp. 1648-1656, 2008.
203. C. Lyden, J. Ryan, C. A. Ugarte, J. Kornblum, and F. M. Yung, "A single shot sigma delta analog to digital converter for multiplexed applications," in Custom Integrated Circuits Conference, 1995, pp. 203-206.
204. P. R. Holloway, E. D. Blom, J. Wan, and S. H. Urie, "Digitizing temperature measurement system and method of operation," US Patent 6 962 436, 2005.
205. C. Jansson, "A high-resolution, compact, and low-power ADC suitable for array implementation in standard CMOS," IEEE Transactions on Circuits and Systems - Part I, vol. 42, no. 11, pp. 904-912, 1995.
206. R. Harjani and T. A. Lee, "FRC: A method for extending the resolution of Nyquist rate converters using oversampling," IEEE Transactions on Circuits and Systems - Part II, vol. 45, no. 4, pp. 482-494, 1998.
207. P. Rombouts, W. D. Wilde, and L. Weyten, "A 13.5-b 1.2-V micropower extended counting A/D converter," IEEE International Journal of Solid State Circuits, vol. 36, no. 2, pp. 176-183, 2001.
208. C. Schott, R. Racz, A. Manco, and N. Simonne, "CMOS single-chip electronic compass with microcontroller," IEEE International Journal of Solid State Circuits, vol. 42, no. 12, pp. 2923-2933, 2007.
209. H.-S. Lee, L. Brooks, and C. G. Sodini, "Zero-crossing-based ultra-low-power A/D converters," Proceedings of the IEEE, vol. 98, no. 2, pp. 315-332, 2010.
210. J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, "Comparator-based switched-capacitor circuits for scaled CMOS technologies," IEEE International Journal of Solid State Circuits, vol. 41, no. 12, pp. 2658-2668, 2006.
211. L. Brooks and H.-S. Lee, "A zero-crossing-based 8-bit 200 MS/s pipelined ADC," IEEE International Journal of Solid State Circuits, vol. 42, no. 12, pp. 2677-2687, 2007.
212. S.-K. Shin, Y.-S. You, S.-H. Lee et al., "A fully-differential zero-crossing-based 1.2V 10 b 26MS/s pipelined ADC in 65 nm CMOS," in VLSI Circuits Conference, 2008, pp. 218-219.
213. T. Musah, S. Kwon, H. Lakdawala, K. Soumyanath, and U.-K. Moon, "A 630 μW zerocrossing- based Δ∑ ADC using switched-resistor current sources in 45 nm CMOS," in Custom Integrated Circuits Conference, 2009, pp. 1-4.
214. L. Brooks and H.-S. Lee, "A 12 b, 50 MS/s, fully differential zero-crossing based pipelined ADC," IEEE International Journal of Solid State Circuits, vol. 44, no. 12, pp. 3329-3343, 2009.
215. L. Brooks and H.-S. Lee, "Background calibration of pipelined ADCs via decision boundary gap estimation," IEEE Transactions on Circuits and Systems - Part I, vol. 55, no. 10, pp. 2969-2979, 2008.
216. T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, "Noise analysis for comparator-based circuits," IEEE Transactions on Circuits and Systems - Part I, vol. 56, no. 3, pp. 541-553, 2009.
217. B. R. Gregoire and U.-K. Moon, "An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain," IEEE International Journal of Solid State Circuits, vol. 43, no. 12, pp. 2620-2630, 2008.
218. K. Nagaraj, "Switched-capacitor circuits with reduced sensitivity to amplifier gain," IEEE Transactions on Circuits and Systems, vol. 34, no. 5, pp. 571-574, 1987.
219. B. Hershberg, S. Weaver, and U.-K. Moon, "Design of a split-CLS pipelined ADC with full signal swing using an accurate but fractional signal swing opamp," IEEE International Journal of Solid State Circuits, vol. 45, no. 12, pp. 2623-2633, 2010.
220. B. R. Veillette and G.W. Roberts, "High frequency sinusoidal generation using delta-sigma modulation techniques," in IEEE International Symposium on Circuits and Systems, 1995, pp. 637-640.
221. E. Roza, "Analog-to-digital conversion via duty-cycle modulation," IEEE Transactions on Circuits and Systems - Part II, vol. 44, no. 11, pp. 907-914, 1997.
222. D. Santos, S. Dow, J. Flasck, and M. Levi, "A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip," IEEE Transactions on Nuclear Science, vol. 43, no. 3, pp. 1717-1727, 1996.
223. G. W. Roberts and M. Ali-Bakhshian, "A brief introduction to time-to-digital and digitalto- time converters," IEEE Transactions on Circuits and Systems - Part II, vol. 57, no. 3, pp. 153-157, 2010.
224. R. E. Best, Ed., Phase-Locked Loops: Design, Simulation and Applications, 4th edn. McGraw-Hill, New York, NY, 1999.
225. P. Dudek, S. Szczepański, and J. V. Hatfield, "A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line," IEEE International Journal of Solid State Circuits, vol. 35, no. 2, pp. 240-247, 2000.
226. S. Sidiropoulos and M. A. Horowitz, "A semidigital dual delay-locked loop," IEEE International Journal of Solid State Circuits, vol. 32, no. 11, pp. 1683-1692, 1997.
227. P. K. Hanumolu, V. Kratyuk, G.-Y. Wei, and U.-K. Moon, "A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter," IEEE International Journal of Solid State Circuits, vol. 43, no. 2, pp. 414-424, 2008.
228. A. Iwata, N. Sakimura, M. Nagata, and T. Morie, "The architecture of delta sigma analogto- digital converters using a voltage-controlled oscillator as a multibit quantizer," IEEE Transactions on Circuits and Systems - Part II, vol. 46, no. 7, pp. 941-945, 1999.
229. Y.-G. Yoon, J. Kim, T.-K. Jang, and S. Cho, "A time-based bandpass ADC using timeinterleaved voltage-controlled oscillators," IEEE Transactions on Circuits and Systems - Part I, vol. 55, no. 11, pp. 3571-3581, 2008.
230. M. Høvin, A. Olsen, T. S. Lande, and C. Toumazou, "A mostly-digital variable-rate continuous-time delta-sigma modulator ADC," IEEE International Journal of Solid State Circuits, vol. 32, no. 1, pp. 13-22, 1997.
231. M. Z. Straayer and M. H. Perrott, "A 12-bit, 10-MHz bandwidth, continuous-timeΔ∑ ADC with a 5-bit, 950-MS/s VCO-based quantizer," IEEE International Journal of Solid State Circuits, vol. 43, no. 4, pp. 805-814, 2008.
232. C. Wulff and T. Ytterdal, "Resonators in open-loop sigma-delta modulators," IEEE Transactions on Circuits and Systems - Part I, vol. 56, no. 10, pp. 2159-2172, 2009.
233. Y.-G. Yoon and S. Cho, "A 1.5-GHz 63 dB SNR 20mW direct RF sampling bandpass VCO-based ADC in 65 nm CMOS," in VLSI Circuits Conference, 2009, pp. 270-271.
234. J. Kim, T.-K. Jang, Y.-G. Yoon, and S. Cho, "Analysis and design of voltage-controlled oscillator based analog-to-digital converter," IEEE Transactions on Circuits and Systems - Part I, vol. 57, no. 1, pp. 18-30, 2010.
235. G. Taylor and I. Galton, "A mostly-digital variable-rate continuous-time delta-sigma modulator ADC," IEEE International Journal of Solid State Circuits, vol. 45, no. 12, pp. 2634-2646, 2010.
236. M. Park and M. H. Perrott, "A 78 dB SNDR 87 mW 20 MHz bandwidth continuoustime Δ∑ ADC with VCO-based integrator and quantizer implemented in 0.13 μ CMOS," IEEE International Journal of Solid State Circuits, vol. 44, no. 12, pp. 3344-3358, 2009.
237. A. Agnes, E. Bonizzoni, P.Malcovati, and F.Maloberti, "A 9.4-ENOB 1V 3.8 μW100 kS/s SARADCwith time-domain comparator," in International Solid-State Circuits Conference, 2008, pp. 246-247.
238. 2 pulse position modulation ADC in 90 nm digital CMOS," IEEE International Journal of Solid State Circuits, vol. 45, no. 9, pp. 1870-1880, 2010.
239. D. Robertson, "The past, present, and future of data converters and mixed signal ICs: A 'universal' model," in VLSI Circuits Conference, 2006, pp. 1-4.
240. B. Murmann and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE International Journal of Solid State Circuits, vol. 38, no. 12, pp. 2040-2050, 2003.
241. W. Yang, D. Kelly, I. Mehr, M. T. Sayuk, and L. Singer, "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input," IEEE International Journal of Solid State Circuits, vol. 36, no. 12, pp. 1931-1936, 2001.
242. A. A. Abidi, A. Matsuzawa, B. Staszewski et al., "A-SSCC 2008 panel on digitally assisted analog and RF circuits: Potentials and issues," in IEEE Asian Solid-State Circuits Conference, IEEE, 2008.
243. A. Baschirotto, "ISSCC 2008 forum on digitally-assisted analog & RF circuits," in International Solid-State Circuits Conference, IEEE, 2008.
244. J. Li and U.-K. Moon, "Background calibration techniques for multistage pipelined ADCs with digital redundancy," IEEE Transactions on Circuits and Systems - Part II, vol. 50, no. 9, pp. 531-538, 2003.
245. E. Siragusa and I. Galton, "A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC," IEEE International Journal of Solid State Circuits, vol. 39, no. 12, pp. 2126-2138, 2004.
246. Y. Chiu, C. W. Tsang, B. Nikolić, and P. R. Gray, "Least mean square adaptive digital background calibration of pipelined analog-to-digital converters," IEEE Transactions on Circuits and Systems - Part I, vol. 51, no. 1, pp. 38-46, 2004.
247. J. P. Keane, P. J. Hurst, and S. H. Lewis, "Background interstage gain calibration technique for pipelined ADCs," IEEE Transactions on Circuits and Systems - Part I, vol. 52, no. 1, pp. 32-43, 2005.
248. J. P. Keane, P. J. Hurst, and S. H. Lewis, "Digital background calibration for memory effects in pipelined analog-to-digital converters," IEEE Transactions on Circuits and Systems - Part I, vol. 53, no. 3, pp. 511-525, 2006.
249. S. Heinen and D. Leenaerts, "ISSCC 2010 forumon reconfigurable RF and data converters," in International Solid-State Circuits Conference, IEEE, 2010.
250. P. Crombez, G. Van der Plas, M. S. J. Steyaert, and J. Craninckx, "A single-bit 500 kHz- 10 MHz multimode power-performance scalable 83-to-67 dB DR CT Δ∑ for SDR in 90 nm digital CMOS," IEEE International Journal of Solid State Circuits, vol. 45, no. 6, pp. 1159-1171, 2010.
251. P. Malla, H. Lakdawala, K. Kornegay, and K. Soumyanath, "A 28mW spectrum-sensing reconfigurable 20MHz72 dB-SNR 70 dB-SNDRDTADCfor 802.11n/WiMAXreceivers," in International Solid-State Circuits Conference, 2008, pp. 496-497.
252. Y. Oh and B.Murmann, "A low-power, 6-bit time-interleaved SAR ADC using OFDM pilot tone calibration," in Custom Integrated Circuits Conference, 2007, pp. 193-196.
253. T. L. Brooks, D. H. Robertson, D. F. Kelly, A. Del Muro, and S. W. Harston, "A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR," IEEE International Journal of Solid State Circuits, vol. 32, no. 12, pp. 1896-1906, 1997.
254. B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, and G. Van der Plas, "A 2.2mW 5 b 1.75 GS/s folding flash ADC in 90 nm digital CMOS," in International Solid-State Circuits Conference, 2008, pp. 252-253.
255. R. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, and G. Van der Plas, "A 2.6mW 6 b 2.2 GS/s 4-times interleaved fully dynamic pipelined ADC in 40 nm digital CMOS," in International Solid-State Circuits Conference, 2010, pp. 296-297.
256. W. C. Black Jr. and D. A. Hodges, "Time interleaved converter arrays," IEEE International Journal of Solid State Circuits, vol. 15, no. 6, pp. 1022-1029, 1980.
257. K. Doris, E. Janssen, C. Nani, A. Zanikopoulos, and G. Van der Weide, "A 480mW 2.6 GS/s 10 b 65 nm CMOS time-interleaved ADC with 48.5 db SNDR up to Nyquist," in International Solid-State Circuits Conference, 2011, pp. 180-181.
258. A. Petraglia and S. K.Mitra, "Analysis ofmismatch effects among A/D converters in a timeinterleaved waveform digitizer," IEEE Transactions on Instrumentation and Measurement, vol. 40, no. 5, pp. 831-835, 1991.
259. N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, "Explicit analysis of channelmismatch effects in time-interleaved ADC systems," IEEE Transactions on Circuits and Systems - Part I, vol. 48, no. 3, pp. 261-271, 2001.
260. C. Vogel, "The impact of combined channel mismatch effects in time-interleaved ADCs," IEEE Transactions on Instrumentation and Measurement, vol. 54, no. 1, pp. 415-427, 2005.
261. D. Fu, K. C. Dyer, S. H. Lewis, and P. J. Hurst, "A digital background calibration technique for time-interleaved analog-to-digital converters," IEEE International Journal of Solid State Circuits, vol. 33, no. 12, pp. 1904-1911, 1998.
262. K. C. Dyer, D. Fu, S. H. Lewis, and P. J. Hurst, "An analog background calibration technique for time-interleaved analog-to-digital converters," IEEE International Journal of Solid State Circuits, vol. 33, no. 12, pp. 1912-1919, 1998.
263. T.-H. Tsai, P. J. Hurst, and S. H. Lewis, "Bandwidth mismatch and its correction in timeinterleaved analog-to-digital converters," IEEE Transactions on Circuits and Systems - Part II, vol. 53, no. 10, pp. 1133-1137, 2006.
264. S. M. Jamal, D. Fu, N. C.-J. Chang, P. J. Hurst, and S. H. Lewis, "A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration," IEEE International Journal of Solid State Circuits, vol. 37, no. 12, pp. 1618-1627, 2002.
265. J. Mulder, F. M. van der Goes, D. Vecchi et al., "An 800 MS/s dual-residue pipeline ADC in 40 nm CMOS," in International Solid-State Circuits Conference, 2011, pp. 184- 185.
266. K. Y. Kim, N. Kusayanagi, and A. A. Abidi, "A 10-b, 100-MS/s CMOS A/D converter," IEEE International Journal of Solid State Circuits, vol. 32, no. 3, pp. 302-311, 1997.
267. H. Jin and E. K. F. Lee, "A digital-background calibration technique for minimizing timingerror effects in time-interleaved ADCs," IEEE Transactions on Circuits and Systems - Part II, vol. 47, no. 7, pp. 603-613, 2000.
268. D. Camarero, K. B. Kalaia, J.-F. Naviner, and P. Loumeau, "Mixed-signal clock-skew calibration technique for time-interleaved ADCs," IEEE Transactions on Circuits and Systems - Part I, vol. 55, no. 11, pp. 3676-3687, 2008.
269. J. Elbornsson and J.-E. Eklund, "Blind estimation of timing errors in interleaved A/D converters," in IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 6, 2001, pp. 3913-3917.
270. J. Elbornsson, F. Gustafsson, and J.-E. Eklund, "Blind equalization of time errors in a time-interleaved ADC system," IEEE Transactions on Signal Processing, vol. 53, no. 4, pp. 1413-1424, 2005.
271. M. Waltari and K. Halonen, "Timing skew insensitive switching for double sampled circuits," in IEEE International Symposium on Circuits and Systems, vol. 1, 1999, pp. 61-64.
272. M. Gustavsson and N. N. Tan, "Explicit analysis of channel mismatch effects in timeinterleaved ADC systems," IEEE Transactions on Circuits and Systems - Part II, vol. 47, no. 9, pp. 821-831, 2000.
273. G. Manganaro, "Feed-forward approach for timing skew in interleaved and double-sampled circuits," US Patent 6 542 017, 2003.
274. S. K. Gupta, M. A. Inerfield, and J. Wang, "A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture," IEEE International Journal of Solid State Circuits, vol. 41, no. 12, pp. 2650-2657, 2006.
275. Y. M. Greshishchev, J. Aguirre, M. Besson et al., "A 40GS/s 6 b ADC in 65 nm CMOS," in International Solid-State Circuits Conference, 2010, pp. 390-391.
276. K. Poulton, K. L. Knudsen, J. Kerley et al., "An 8-GSa/s 8-bit ADC system," in VLSI Circuits Conference, 1997, pp. 23-24.
277. M. Tamba, A. Shimizu, H. Munakata, and T. Komuro, "A method to improve SFDR with random interleaved sampling method," in IEEE International Test Conference, 2001, pp. 512-520.
278. G. Bernardinis, P. Malcovati, F. Maloberti, and E. Soenen, "Dynamic stage matching for parallel pipeline A/D converters," in IEEE International Symposium on Circuits and Systems, vol. 1, 2002, pp. 905-909.
279. K. El-Sankary, A. Assi, and M. Sawan, "New sampling method to improve the SFDR of time-interleaved ADCs," in IEEE International Symposium on Circuits and Systems, vol. 1, 2003, pp. 833-836.
280. J. Elbornsson, F. Gustafsson, and J.-E. Eklund, "Analysis of mismatch effects in a randomly interleaved A/D converter system," IEEE Transactions on Circuits and Systems - Part I, vol. 52, no. 3, pp. 465-476, 2005.
281. I. Galton, "Digital cancellation of D/A converter noise in pipelined A/D converters," IEEE Transactions on Circuits and Systems - Part II, vol. 47, no. 3, pp. 185-196, 2000.
282. E. J. Siragusa and I. Galton, "Gain error correction technique for pipelined analogue-todigital converters," IEE Electronics Letters, vol. 36, no. 7, pp. 617-618, 2000.
283. X. Wang, P. J. Hurst, and S. H. Lewis, "A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration," IEEE International Journal of Solid State Circuits, vol. 39, no. 9, pp. 1799-1808, 2004.
284. C. R. Grace, P. J. Hurst, and S. H. Lewis, "A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration," IEEE International Journal of Solid State Circuits, vol. 40, no. 5, pp. 1038-1046, 2005.
285. N. Sun, H.-S. Lee, and D. Ham, "Digital background calibration in pipelined ADCs using commutated feedback capacitor switching," IEEE Transactions on Circuits and Systems - Part II, vol. 55, no. 9, pp. 877-881, 2008.
286. H. Wang, X. Wang, P. J. Hurst, and S. H. Lewis, "Nested digital background calibration of a 12-bit pipelined ADC without an input SHA," IEEE International Journal of Solid State Circuits, vol. 44, no. 10, pp. 2780-2789, 2009.
287. I. Mehr and L. Singer, "A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC," IEEE International Journal of Solid State Circuits, vol. 35, no. 3, pp. 318-325, 2000.
288. D.-Y. Chang, "Design techniques for a pipelined ADC without using a front-end sampleand- hold amplifier," IEEE Transactions on Circuits and Systems - Part I, vol. 51, no. 11, pp. 2123-2132, 2004.
289. M. Yoshioka, M. Kudo, K. Gotoh, and Y. Watanabe, "A 10 b 125 MS/s 40mW pipelined ADC in 0.18 μm CMOS," in International Solid-State Circuits Conference, 2005, pp. 282- 283.
290. 2 10 b 30 MS/s pipelined ADC without a front-end S/H in 90 nm CMOS," in International Solid- State Circuits Conference, 2007, pp. 456-457.
291. B.-G. Lee, B.-M. Min, G. Manganaro, and J.W. Valvano, "A 14-b 100-MS/s pipelined ADC with a merged SHA and first MDAC," IEEE International Journal of Solid State Circuits, vol. 43, no. 12, pp. 2613-2619, 2008.
292. B.-M. Min, P. Kim, F. W. Bowman III, D. M. Boisvert, and A. J. Aude, "A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC," IEEE International Journal of Solid State Circuits, vol. 38, no. 12, pp. 2031-2039, 2003.
293. M. Yoshioka, M. Kudo, K. Gotoh, and Y. Watanabe, "A1.8 v 10 b 210 MS/s CMOSpipelined ADCfeaturing 86 dBSFDRwithout calibration," in Custom Integrated Circuits Conference, 2007, pp. 317-320.
294. D. Gubbins, B. Lee, P. K. Hanumolu, and U.-K. Moon, "Continuous-time input pipeline ADCs," IEEE International Journal of Solid State Circuits, vol. 45, no. 8, pp. 1456-1468, 2010.
295. C. A. A. Bastiaansen, D. W. J. Groeneveld, H. J. Schouwenaars, and H. A. H. Termeer, "A 10-b 40-MHz 0.8-μm CMOS current-output D/A converter," IEEE International Journal of Solid State Circuits, vol. 26, no. 7, pp. 917-921, 1991.
296. C. Toumazou, J. B. Hughes, and N. C. Battersby, Eds., Switched-Currents: An Analogue Technique for Digital Technology. Peter Peregrinus Ltd., on behalf of the IEE, London, UK, 1993.
297. A. R. Bugeja, B.-S. Song, P. L. Rakers, and S. F. Gillig, "A 14-b, 100-MS/s CMOS DAC designed for spectral performance," IEEE International Journal of Solid State Circuits, vol. 34, no. 12, pp. 1719-1732, 1999.
298. W. Schofield, D. Mercer, and L. St. Onge, "A 16 b 400 MS/s DAC with < −80 dBc IMD to 300MHz and < −160 dBm/Hz noise power spectral density," in International Solid-State Circuits Conference, 2003, pp. 126-127.
299. M. Clara, W. Klatzer, A. Wiesbauer, and D. Straeussnigg, "A 350MHz low-OSR Δ∑ current-steering DAC with active termination in 0.13 μm CMOS," in International Solid- State Circuits Conference, 2005, pp. 118-119.
300. B. Nejati and L. Larson, "An area optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DAC," in Custom Integrated Circuits Conference, 2006, pp. 161-164.
301. B. Jewett, J. Liu, and K. Poulton, "A 1.2 GS/s 15-bit DAC for precision signal generation," in International Solid-State Circuits Conference, 2005, pp. 110-111.
302. M.-J. Choe, K.-H. Baek, and M. Teshome, "A 1.6 GS/s 12 b return-to-zero GaAs RF DAC for multiple Nyquist operation," in International Solid-State Circuits Conference, 2005, pp. 112-113.
303. P. Schvan, D. Pollex, and T. Bellingrath, "A 22 GS/s 6 b DAC with integrated digital ramp generator," in International Solid-State Circuits Conference, 2005, pp. 122-123.
304. D. Baranauskas and D. Zelenin, "A0.36W6 b up to 20GS/sDACforUWBwave formation," in International Solid-State Circuits Conference, 2006, pp. 580-581.
305. 2 die area," IEEE Transactions on Circuits and Systems - Part II, vol. 52, no. 5, pp. 246-250, 2005.
306. 2," IEEE International Journal of Solid State Circuits, vol. 33, no. 12, pp. 1948-1958, 1998.
307. G. I. Radulov, M. Heydenreich, R. W. van Hofstad, J. A. Hegt, and A. H. M. von Roermund, "Brownian-bridge-based statistical analysis of the DAC INL caused by current mismatch," IEEE Transactions on Circuits and Systems - Part II, vol. 54, no. 2, pp. 146-150, 2007.
308. S. Luschas and H.-S. Lee, "Output impedance requirements for DACs," in IEEE International Symposium on Circuits and Systems, vol. 1, 2003, pp. 861-864.
309. P. Crippa, C. Turchetti, and M. Conti, "A statistical methodology for the design of highperformance CMOS current-steering digital-to-analog converters," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 4, pp. 377-394, 2002.
310. C. S. G. Conroy, W. A. Lane, and M. A. Moran, "Statistical design techniques for D/A converters," IEEE International Journal of Solid State Circuits, vol. 24, no. 4, pp. 1118- 1128, 1989.
311. B. Schafferer and R. Adams, "A 3V CMOS 400mW 14 b 1.4 GS/s DAC for multicarrier applications," in International Solid-State Circuits Conference, 2004, pp. 360- 361.
312. 2 random walk CMOS DAC," IEEE International Journal of Solid State Circuits, vol. 34, no. 12, pp. 1708-1718, 1999.
313. Y. Cong and R. L. Geiger, "Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays," IEEE Transactions on Circuits and Systems - Part II, vol. 47, no. 7, pp. 585-595, 2000.
314. M. Vadipour, "Gradient error cancellation and quadratic error reduction in unary and binary D/A converters," IEEE Transactions on Circuits and Systems - Part II, vol. 50, no. 12, pp. 1002-1007, 2003.
315. 2 I switched-current multiplier," IEEE Transactions on Circuits and Systems-Part II, vol. 45, no. 7, pp. 791-799, 1998.
316. A. R. Bugeja and B.-S. Song, "A self-trimming 14-b, 100-MS/s CMOS DAC," IEEE International Journal of Solid State Circuits, vol. 35, no. 12, pp. 1841-1852, 2000.
317. Q. Huang, P. A. Francese, C. Martelli, and J. Nielsen, "A 200 MS/s 14 b 97mW DAC in 0.18 μm CMOS," in International Solid-State Circuits Conference, 2004, pp. 364-365.
318. G. Manganaro, "Analog calibration of a current source array at low supply voltage," US Patent 7 161 412, 2007.
319. G. Manganaro, "Transresistance amplifier," US Patent 7 202 744, 2007.
320. Y. Tang, J. Briaire, K. Doris et al., "A 14 b 200 MS/s DAC with SFDR>78 dBc, IM3< −83 dBc and NSD< −163 dBm/Hz across the whole Nyquist band enabled by dynamicmismatch mapping," in VLSI Circuits Conference, 2010, pp. 151-152.
321. W.-H. Tseng, C.-W. Fan, and J.-T. Wu, "A 12-bit 1.25-GS/s DAC in 90 nm CMOS with > 70 dB SFDR up to 500 MHz," in International Solid-State Circuits Conference, 2011, pp. 192-193.
322. W.-H. Tseng, J.-T. Wu, and C.-W. Fan, "A CMOS 8-bit 1.6 GS/s DAC with digital random return-to-zero," IEEE Transactions on Circuits and Systems - Part II, vol. 58, no. 1, pp. 1-5, 2011.
323. J. Hyde, T. Humes, C. Diorio, M. Thomas, and M. Figueroa, "A 300-MS/s 14-bit digitalto- analog converter in logic CMOS," IEEE International Journal of Solid State Circuits, vol. 38, no. 5, pp. 734-740, 2003.
324. D. Marche, Y. Savaria, and Y. Gagnon, "Laser fine-tuneable deep-submicrometer CMOS 14-bit DAC," IEEE Transactions on Circuits and Systems - Part I, vol. 55, no. 8, pp. 2157-2165, 2008.
325. D. Mercer and L. Singer, "A 12-b 125 MSPS CMOS D/A designed for spectral performance," in IEEE International Symposium on Low Power Electronics and Design, 1996, pp. 243-246.
326. A. Van den Bosch, M. S. J. Steyaert, and W. Sansen, "SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters," in International Conference on Electronics, Circuits and Systems, vol. 3, 1999, pp. 1193-1196.
327. J. Deveugele and M. S. J. Steyaert, "RF DAC's: Output impedance and distortion," in RF Circuits: Wide Band, Front-Ends, DAC's, Design Methodology and Verification for RF and Mixed-Signal Systems, Low Power and Low Voltage, M. Steyaert, A. van Roermund, and J. H. Huijsing, Eds. Kluwer, Dordrecht, the Netherlands, 2006, pp. 45-64.
328. A. van den Bosch, M. Steyaert, and W. M. Sansen, Static and Dynamic Performance Limitations for High Speed D/A Converters. Kluwer, Dordrecht, the Netherlands, 2004.
329. A. Van den Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, "A 10-b, 1- GSample/s Nyquist current-steering CMOS D/A converter," IEEE International Journal of Solid State Circuits, vol. 36, no. 3, pp. 315-324, 2001.
330. J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 12-bit intrinsic accuracy high-speed CMOS DAC," IEEE International Journal of Solid State Circuits, vol. 33, no. 12, pp. 1959-1969, 1998.
331. M. Clara, A. Wiesbauer, and W. Klatzer, "Nonlinear distortion in current-steering D/Aconverters due to asymmetrical switching errors," in IEEE International Symposium on Circuits and Systems, vol. 1, 2004, pp. 285-289.
332. G. Manganaro, "Current steering digital to analog converter with improved dynamic linearity," US Patent 7 023 367, 2006.
333. D. Seo and G. H. McAllister, "A low-spurious low-power 12-bit 160-MS/s DAC in 90- nm CMOS for baseband wireless transmitter," IEEE International Journal of Solid State Circuits, vol. 42, no. 3, pp. 486-495, 2007.
334. K. Doris, J. Briaire, D. Leenaerts, M. Vertregt, and A. van Roermund, "A 12 b 500 MS/s DAC with > 70 dB SFDR up to 120MHz in 0.18 μm CMOS," in International Solid-State Circuits Conference, 2005, pp. 116-117.
335. K. Doris, A. H. M. van Roermund, and D. Leenaerts, Wide-Bandwidth High Dynamic Range D/A Converters. Springer-Verlag, Berlin, Germany, 2010.
336. M. Alioto and G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits. Kluwer, Dordrecht, the Netherlands, 2010.
337. B. Schafferer, "Control loop for minimal tailnode excursion of differential switches," US Patent 6 774 683, 2004.
338. S. Park, G. Kim, S.-C. Park, and W. Kim, "A digital-to-analog converter based on differential-quad switching," IEEE International Journal of Solid State Circuits, vol. 37, no. 10, pp. 1335-1338, 2002.
339. B. Schafferer, "Constant switching for signal processing," US Patent 6 842 132, 2005.
340. S. H. Hall, G. W. Hall, and J. A. McCall, High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices. John Wiley & Sons, New York, NY, 2000.
341. T. Chen and G. G. E. Gielen, "The analysis and improvement of a current-steering DACs dynamic SFDR - I: The cell-dependent delay differences," IEEE Transactions on Circuits and Systems - Part I, vol. 53, no. 1, pp. 3-15, 2006.
342. T. Chen and G. G. E. Gielen, "The analysis and improvement of a current-steering DAC's dynamic SFDR - II: The output-dependent delay differences," IEEE Transactions on Circuits and Systems - Part I, vol. 54, no. 2, pp. 268-279, 2007.
343. D. Mercer, "Latch with data jitter free clock load," US Patent 7 023 255, 2006.
344. D. Mercer, "Alowpower current steering digital to analog converter in 0.18 micron CMOS," in IEEE International Symposium on Low Power Electronics and Design, 2005, pp. 72-77.
345. A. R. Bugeja, "High dynamic linearity current-mode digital-to-analog converter architecture," US Patent 6 906 652, 2005.
346. K. Gulati, M. S. Peng, A. Pulincherry et al., "A highly integrated CMOS analog baseband transceiver with 180 MSPS 13-bit pipelined CMOS ADC and dual 12-bit DACs," IEEE International Journal of Solid State Circuits, vol. 41, no. 8, pp. 1856-1866, 2006.
347. J. Deveugele and M. S. J. Steyaert, "A 10-b 250 MS/s binary-weighted current steering DAC," IEEE International Journal of Solid State Circuits, vol. 41, no. 2, pp. 320-329, 2006.
348. X.Wu, P. Palmers, and M. S. J. Steyaert, "A 130 nm CMOS 6-bit full Nyquist 3 GS/s DAC," IEEE International Journal of Solid State Circuits, vol. 43, no. 11, pp. 2396-2403, 2008.
349. R. W. Adams and K. Q. Nguyen, "Dual return-to-zero pulse encoding in a DAC output stage," US Patent 6 061 010, 1997.
350. R. Adams, K. Q. Nguyen, and K. Sweetland, "A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling," IEEE International Journal of Solid State Circuits, vol. 33, no. 12, pp. 1871-1878, 1998.
351. 2," IEEE International Journal of Solid State Circuits, vol. 39, no. 7, pp. 1064-1072, 2004.
352. X. Wu, P. Palmers, and M. S. J. Steyaert, "An 80-MHz 8-bit CMOS D/A converter," IEEE International Journal of Solid State Circuits, vol. 21, no. 6, pp. 983-988, 1986.
353. T. W. Kwan, R. W. Adams, and R. Libert, "A stereo multibit sigma delta DAC with asynchronous master-clock interface," IEEE International Journal of Solid State Circuits, vol. 31, no. 12, pp. 1881-1887, 1996.
354. K. Nguyen, A. Bandyopadhyay, R. Adams, K. Sweetland, and P. Baginski, "A 108 dB SNR 1.1mW oversampling audio DAC with a three-level DEM technique," IEEE International Journal of Solid State Circuits, vol. 43, no. 12, pp. 2592-2600, 2008.
355. P. Rombouts and L. Weyten, "Dynamic element matching for pipelined A/D conversion," in IEEE International Conference on Electronics, Circuits, and Systems, vol. 2, 1998, pp. 315-318.
356. K. L. Chan, J. Zhu, and I. Galton, "Dynamic element matching to prevent nonlinear distortion from pulse-shape mismatches in high-resolution DACs," IEEE International Journal of Solid State Circuits, vol. 43, no. 9, pp. 2067-2078, 2008.
357. T. Shui, R. Schreier, and F. Hudson, "Modified mismatch-shaping for continuous-time delta-sigma modulators," in Custom Integrated Circuits Conference, 1998, pp. 225- 228.
358. T. Shui, R. Schreier, and F. Hudson, "Mismatch shaping for a current-mode multibit delta- sigma DAC," IEEE International Journal of Solid State Circuits, vol. 34, no. 3, pp. 331-338, 1999.
359. A. Fishov, E. Siragusa, J. Web, E. Fogleman, and I. Galton, "Segmented mismatch shaping D/A conversion," in IEEE International Symposium on Circuits and Systems, vol. 4, 2002, pp. 679-682.
360. B. Nordick, C. Petrie, and Y. Cheng, "Dynamic element matching techniques for delta- sigma ADCs with large internal quantizers," in IEEE International Symposium on Circuits and Systems, vol. 1, 2004, pp. 653-656.
361. Y. Cheng, C. Petrie, B. Nordick, and D. Comer, "Multibit delta-sigma modulator with two-step quantization and segmented DAC," IEEE Transactions on Circuits and Systems - Part II, vol. 53, no. 9, pp. 848-852, 2006.
362. K. L. Chan and I. Galton, "A 14 b 100 MS/s DAC with fully segmented dynamic element matching," in International Solid-State Circuits Conference, 2006, pp. 582-583.
363. K. L. Chan, J. Zhu, and I. Galton, "A 150 MS/s 14-bit segmented DEM DAC with greater than 83 dB of SFDR across the Nyquist band," in VLSI Circuits Conference, 2007, pp. 200-201.
364. K. L. Chan, N. Rakulijc, and I. Galton, "Segmented dynamic element matching for highresolution digital-to-analog conversion," IEEE Transactions on Circuits and Systems - Part I, vol. 55, no. 11, pp. 3383-3392, 2008.
365. T. Lin and H. Samueli, "A 200-MHz CMOS x/sin(x) digital filter for compensating D/A converter frequency response distortion," IEEE International Journal of Solid State Circuits, vol. 26, pp. 1278-1285, 1991.
366. A. K. Gupta, J. Venkataraman, and O. M. Collins, "Measurement and reduction of ISI in high-dynamic-range 1-bit signal generation," IEEE Transactions on Circuits and Systems - Part I, vol. 55, no. 11, pp. 3593-3606, 2008.
367. Y. Li and B. Schafferer, "Mixer/DAC chip and method," International Patent WO 2008/112 348 A1, 2008.
368. Y. Li and B. Schafferer, "Mixer/DAC chip and method," US Patent 7 796 971, 2010.
369. P. T. M. van Zeijl and M. Collados, "On the attenuation of DAC aliases through multiphase clocking," IEEE Transactions on Circuits and Systems - Part II, vol. 56, no. 3, pp. 190-194, 2009.
370. Y. Zhou and J. Yuan, "A 10-bit wide-band CMOS direct digital RF amplitude modulator," IEEE International Journal of Solid State Circuits, vol. 38, no. 7, pp. 1182-1188, 2003.
371. J. Deveugele, P. Palmers, and M. S. J. Steyaert, "Parallel-path digital-to-analog converters for Nyquist signal generation," IEEE International Journal of Solid State Circuits, vol. 39, no. 7, pp. 1073-1082, 2004.
372. J. Franca, A. Petraglia, and S. K. Mitra, "Multirate analog-digital systems for signal processing and conversion," Proceedings of the IEEE, vol. 85, no. 2, pp. 242-262, 1997.
373. Analog Devices Staff, "A technical tutorial on digital signal synthesis," Analog Devices, Application Note, 1999.
374. K. Lee, Q. Meng, T. Sugimoto et al., "A 0.8 V, 2.6 mW, 88 dB dual-channel audio delta- sigma D/A converter with headphone driver," IEEE International Journal of Solid State Circuits, vol. 44, no. 3, pp. 916-927, 2009.
375. out," IEEE International Journal of Solid State Circuits, vol. 40, no. 7, pp. 1491-1498, 2005.
376. K. Nguyen and R. Schreier, "System and method for tri-level logic data shuffling for oversampling data conversion," US Patent 7 079 063, 2006.
377. A. Bandyopadhyay, M. Determan, S. Kim, and K. Nguyen, "A 120 dB SNR, 100 dB THD+N, 21.5 mW/channel multibit continuous time Δ∑ DAC," in International Solid- State Circuits Conference, 2011, pp. 482-483.
378. R. Hezar, L. Risbo, H. Kiper et al., "A 110 dB SNR and 0.5mWcurrent-steering audio DAC implemented in 45 nm CMOS," in International Solid-State Circuits Conference, 2010, pp. 304-307.
379. L. Risbo, R. Hezar, B. Kelleci, H. Kiper, and M. Fares, "A 108 dB DR, 120 dB THD and 0.5Vrms output audio DAC with inter-symbol-interference shaping algorithm in 45 nm," in International Solid-State Circuits Conference, 2011, pp. 484-485.
380. J. Vankka, Digital Synthesizers and Transmitters for Software Radio, 1st edn. Springer- Verlag, Berlin, Germany, July 2005.
381. H. T. Nicholas III and H. Samueli, "A 150-MHz direct digital frequency synthesizer in 1.25-μm CMOS with -90-dBc spurious performance," IEEE International Journal of Solid State Circuits, vol. 26, no. 12, pp. 1959-1969, 1991.
382. D. De Caro, N. Petra, and A. G. M. Strollo, "A 380 MHz direct digital synthesizer/mixer with hybrid CORDIC architecture in 0.25 μm CMOS," IEEE International Journal of Solid State Circuits, vol. 42, no. 1, pp. 151-160, 2007.
383. C. Y. Kang and E. E. Swartzlander Jr., "Digit-pipelined direct digital frequency synthesis based on differential CORDIC," IEEE Transactions on Circuits and Systems - Part I, vol. 53, no. 5, pp. 1035-1044, 2006.
384. A. Ashrafi, R. Adhami, and A. Milenković, "A direct digital frequency synthesizer based on the quasi-linear interpolation method," IEEE Transactions on Circuits and Systems - Part I, vol. 57, no. 4, pp. 863-872, 2010.
385. D. De Caro and A. G. M. Strollo, "High-performance direct digital frequency synthesizers in 0.25 μm CMOS using dual-slope approximation," IEEE International Journal of Solid State Circuits, vol. 40, no. 11, pp. 2220-2227, 2005.
386. F. F. Dai, W. Ni, S. Yin, and R. C. Jaeger, "A direct digital frequency synthesizer with fourthorder phase domain Δ∑ noise shaper and 12-bit current-steering DAC," IEEE International Journal of Solid State Circuits, vol. 41, no. 4, pp. 839-850, 2006.
387. A. McEwan and S. Collins, "Direct digital-frequency synthesis by analog interpolation," IEEE Transactions on Circuits and Systems - Part II, vol. 53, no. 11, pp. 1294-1298, 2006.
388. S. Thuries, E. Tournier, A. Cathelin, S. Godet, and J. Graffeuil, "A 6-GHz low-power BiCMOS SiGe:C 0.25 μm direct digital synthesizer," IEEE Microwave and Wireless Components Letters, vol. 18, no. 1, pp. 46-48, 2008.
389. S. Mortezapour and E. K. F. Lee, "Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter," IEEE International Journal of Solid State Circuits, vol. 34, no. 10, pp. 1350-1359, 1999.
390. J. Jiang and E. K. F. Lee, "A low-power segmented nonlinear DAC-based direct digital frequency synthesizer," IEEE International Journal of Solid State Circuits, vol. 37, no. 10, pp. 1326-1330, 2002.
391. S. E. Turner and D. E. Kotecki, "Direct digital synthesizer with sine-weighted DAC at 32-GHz clock frequency in In P DHBT technology," IEEE International Journal of Solid State Circuits, vol. 41, no. 10, pp. 2284-2290, 2006.
392. Z. Zhou and G. S. L. Rue, "A 12-bit nonlinear DAC for direct digital frequency synthesis," IEEE Transactions on Circuits and Systems - Part I, vol. 55, no. 9, pp. 2459-2468, 2008.
393. X. Geng, F. F. Dai, J.D. Irwin, and R. C. Jaeger, "An 11-bit 8.6 GHz direct digital synthesizer MMIC with 10-bit segmented sine-weighted DAC," IEEE International Journal of Solid State Circuits, vol. 45, no. 2, pp. 300-313, 2010.
394. H. C. Yeoh, J.-H. Jung, Y.-H. Jung, and K.-H. Baek, "A 1.3-GHz 350-mW hybrid direct digital frequency synthesizer in 90-nm CMOS," IEEE International Journal of Solid State Circuits, vol. 45, no. 9, pp. 1845-1855, 2010.
395. J. Savoj, A. Abbasfar, A. Amirkhany, M. Jeeradit, and B. W. Garlepp, "A 12-GS/s phasecalibrated CMOS digital-to-analog converter for backplane communications," IEEE International Journal of Solid State Circuits, vol. 43, no. 5, pp. 1207-1216, 2008.
396. S. Luschas, R. Schreier, and H.-S. Lee, "Radio frequency digital-to-analog converter," IEEE International Journal of Solid State Circuits, vol. 39, no. 9, pp. 1462-1467, 2004.
397. S. Luschas and H.-S. Lee, "High-speed Δ∑ modulators with reduced timing jitter sensitivity," IEEE Transactions on Circuits and Systems - Part II, vol. 49, no. 11, pp. 712-720, 2002.
398. P. Eloranta and P. Seppinen, "Direct-digital RF modulator IC in 0.13 μm CMOS for wideband multi-radio applications," in International Solid-State Circuits Conference, 2005, pp. 532-533.
399. A. Jerng and C. G. Sodini, "A wideband Δ∑ digital-RF modulator for high data rate transmitters," IEEE International Journal of Solid State Circuits, vol. 42, no. 8, pp. 1710- 1722, 2007.
400. B. Razavi, RF Microelectronics. Prentice Hall, New York, NY, 1998.
401. P. Eloranta, P. Seppinen, S. Kallioinen, T. Saarela, and A. Pärssinen, "A multimode transmitter in 0.13 μm CMOS using direct-digital RF modulator," IEEE International Journal of Solid State Circuits, vol. 42, no. 12, pp. 2774-2784, 2007.
402. N. Zimmermann, R. Negra, and S. Heinen, "Design of an RF-DAC in 65 nm CMOS for multistandard, multimode transmitters," in IEEE International Symposium on Radio- Frequency Integration Technology, 2009, pp. 343-346.
403. S. M. Taleie, T. Copani, B. Bakkaloglu, and S. Kiaei, "A linear ∑-Δ digital IF to RF DAC transmitter with embedded mixer," IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 5, pp. 1059-1068, 2008.
404. M. Park, M. H. Perrott, and R. B. Staszewski, "A time-domain resolution improvement of an RF-DAC," IEEE Transactions on Circuits and Systems - Part II, vol. 57, no. 7, pp. 517-521, 2010.
405. B. E. Jonsson, "A survey of A/D-converter performance evolution," in IEEE International Conference on Electronics, Circuits, and Systems, 2010, pp. 768-771.
406. T. Sundström, B. Murmann, and C. Svensson, "Power dissipation bounds for high-speed Nyquist analog-to-digital converters," IEEE Transactions on Circuits and Systems - Part I, vol. 56, no. 3, pp. 509-518, 2009.
407. J.-Y. Wu, R. Subramoniam, Z. Zhang et al., "Multi-bit sigma delta ADC with reduced feedback levels, extended dynamic range and increased tolerance for analog imperfections," in Custom Integrated Circuits Conference, 2007, pp. 77-80.
408. B. J. Farahani, S. G. Krishna, S. Venkatesan et al., "Wide-temperature high-resolution integrated data acquisition for spectroscopy in space," in IEEE Aerospace Conference, 2011.
409. A. Sheikholeslami, R. Payne, and J. Lin, "ISSCC 2009 evening session on 'will ADCs overtake binary frontends in backplane signaling?'," in International Solid-State Circuits Conference, IEEE, 2 2009.
410. E.-H. Chen and C.-K. K. Yang, "ADC-based serial I/O receivers," IEEE Transactions on Circuits and Systems - Part I, vol. 57, no. 9, pp. 2248-2258, 2010.
411. A. Wegener, "Compression of medical sensor data [exploratory DSP]," IEEE Signal Processing Magazine, vol. 27, no. 4, pp. 125-130, 2010.
412. P. Löwenborg, H. Johansson, and L. Wanhammar, "Two-channel digital and hybrid analog/digital multirate filter banks with very low-complexity analysis or synthesis filters," IEEE Transactions on Circuits and Systems - Part II, vol. 50, no. 7, pp. 355-367, 2003.
413. H. Johansson and P. Löwenborg, "A least-squares filter design technique for the compensation of frequency response mismatch errors in time-interleaved A/D converters," IEEE Transactions on Circuits and Systems - Part II, vol. 55, no. 11, pp. 1154-1158, 2008.
414. W. Xiong, U. Zschieschang, H. Klauk, and B.Murmann, "A3V6b successive-approximation ADC using complementary organic thin-film transistors on glass," in International Solid- State Circuits Conference, 2010, pp. 134-135.
415. H. Marien, M. Steyaert, N. van Aerle, and P. Heremans, "An analog organic first-order ct Δ∑ ADC on a flexible plastic substrate with 26.5 dB precision," in International Solid-State Circuits Conference, 2010, pp. 136-137.
416. T. Zaki, F. Ante, U. Zschieschang, J. Butschke, F. Letzkus, H. Richter, H. Klauk, and J. N. Burghartz, "A 3.3 V 6b 100 kS/s current-steering D/A converter using organic thin-film transistors on glass," in International Solid-State Circuits Conference, 2011, pp. 324-325.