A 7bit 800Msps 120mW folding and interpolation ADC using a mixed-averaging scheme

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 138-139

  Makigawa, Kiyoshi ^a   Ono, Koichi ^a   Ohkawa, Takeshi ^a   Matsuura, Kouji ^a   Segami, Masahiro ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; INTERPOLATION; SIGNAL TO NOISE RATIO;

COMPARATOR STAGE; INTERPOLATION STAGES;

ANALOG TO DIGITAL CONVERSION;

EID: 34250213328     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. M. Flynn and D. Allstot, "CMOS Folding A/D Converters with Current-Mode Interpolation," IEEE J. Solid-State Circuits, vol. 31, pp. 1248-1257, Sep. 1996.
2. H. Pan, and A. A. Abidi, "Spatial Filtering in Flash A/D Converters," IEEE Trans. Circuits and Syst.-II: Analog and Digital Signal Processing, vol. 50, pp. 424-436, Aug. 2003.
3. S. Tsukamoto, W. G Schofield, and T. Endo, "A CMOS 6-b 400-MSamples/s ADC with Error Correction," IEEE J. Solid-State Circuits, vol. 33, pp. 1939-1947, Dec. 1998.