-
2
-
-
49549103790
-
A 150 MS/s 133 μW 7 bit ADC in 90 nm digital CMOS using a comparator-based asynchronous binary-search sub-ADC
-
G. Van der Plas and B. Verbruggen, "A 150 MS/s 133 μW 7 bit ADC in 90 nm digital CMOS using a comparator-based asynchronous binary-search sub-ADC", in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 242-243.
-
(2008)
IEEE ISSCC Dig. Tech. Papers
, pp. 242-243
-
-
Van der Plas, G.1
Verbruggen, B.2
-
3
-
-
2442692681
-
A 6b 600 MHz 10 mW ADC array in digital 90 nm CMOS
-
D. Draxelmayr, "A 6b 600 MHz 10 mW ADC array in digital 90 nm CMOS", in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 264-265.
-
(2004)
IEEE ISSCC Dig. Tech. Papers
, pp. 264-265
-
-
Draxelmayr, D.1
-
4
-
-
34547154701
-
A 0.16 pF/conversion-step 2.5 mW 1.25 GS/s 4b ADC in a 90 nm digital CMOS process
-
Feb
-
G. Van der Plas et al., "A 0.16 pF/conversion-step 2.5 mW 1.25 GS/s 4b ADC in a 90 nm digital CMOS process", in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 566-567.
-
(2006)
IEEE ISSCC Dig. Tech. Papers
, pp. 566-567
-
-
Van der Plas, G.1
-
5
-
-
34548850306
-
A 65 fJ/conversion-step, 0-50 MS/s 0-0.7 mW 9bit charge-sharing SAR ADC in 90 nm digital CMOS
-
Feb
-
J. Craninckx et al., "A 65 fJ/conversion-step, 0-50 MS/s 0-0.7 mW 9bit charge-sharing SAR ADC in 90 nm digital CMOS", in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 246-247.
-
(2007)
IEEE ISSCC Dig. Tech. Papers
, pp. 246-247
-
-
Craninckx, J.1
-
6
-
-
49549118053
-
An 820 μWW 9b 40 MS/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS
-
Feb
-
V. Giannini et al., "An 820 μWW 9b 40 MS/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 238-239.
-
(2008)
IEEE ISSCC Dig. Tech. Papers
, pp. 238-239
-
-
Giannini, V.1
-
7
-
-
49549089559
-
A 2.2 mW 5b 1.75 GS/s folding flash ADC in 90 nm digital CMOS
-
Feb
-
B. Verbruggen et al., "A 2.2 mW 5b 1.75 GS/s folding flash ADC in 90 nm digital CMOS", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 252-253.
-
(2008)
IEEE ISSCC Dig. Tech. Papers
, pp. 252-253
-
-
Verbruggen, B.1
-
8
-
-
49549117124
-
A 1.2 V 4.5 mW 10 b 100 MS/s pipelined ADC in 65 nm CMOS
-
Feb
-
M. Boulemnakher et al., "A 1.2 V 4.5 mW 10 b 100 MS/s pipelined ADC in 65 nm CMOS", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 250-251.
-
(2008)
IEEE ISSCC Dig. Tech. Papers
, pp. 250-251
-
-
Boulemnakher, M.1
-
9
-
-
49549109409
-
A 1.9 μW 4.4 fJ/conversion-step 10b 1 MS/s charge-redistribution ADC
-
Feb
-
M. van Elzakker et al., "A 1.9 μW 4.4 fJ/conversion-step 10b 1 MS/s charge-redistribution ADC", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008. pp. 244-245.
-
(2008)
IEEE ISSCC Dig. Tech. Papers
, pp. 244-245
-
-
van Elzakker, M.1
-
10
-
-
0036917305
-
A 6-b 1.6-Gsamples flash ADC in 0.18 μm CMOS using averaging termination
-
Dec
-
P. Scholtens and M. Vertregt, "A 6-b 1.6-Gsamples flash ADC in 0.18 μm CMOS using averaging termination", IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1599-1609, Dec. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.12
, pp. 1599-1609
-
-
Scholtens, P.1
Vertregt, M.2
-
11
-
-
0036912822
-
An embedded 0.8 V/480 μW 6B/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique
-
Dec
-
J. Lin and B. Haroun, "An embedded 0.8 V/480 μW 6B/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique", IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1610-1617, Dec. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.12
, pp. 1610-1617
-
-
Lin, J.1
Haroun, B.2
-
12
-
-
49549121397
-
Highly interleaved 5b 250 MS/s ADC with redundant channels in 65 nm CMOS
-
Feb
-
B. P. Ginsburg and A. P. Chandrakasan, "Highly interleaved 5b 250 MS/s ADC with redundant channels in 65 nm CMOS", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 240-241.
-
(2008)
IEEE ISSCC Dig. Tech. Papers
, pp. 240-241
-
-
Ginsburg, B.P.1
Chandrakasan, A.P.2
-
13
-
-
33845655208
-
A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS
-
Dec
-
S. Chen and R. Brodersen, "A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS", IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.12
, pp. 2669-2680
-
-
Chen, S.1
Brodersen, R.2
-
14
-
-
57849161405
-
A zero-crossing-based 8-bit 200 MS/s pipelined ADC
-
Dec
-
L. Brooks and H.-S. Lee, "A zero-crossing-based 8-bit 200 MS/s pipelined ADC", IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 1896-1906, Dec. 2007.
-
(2007)
IEEE J. Solid-State Circuits
, vol.42
, Issue.12
, pp. 1896-1906
-
-
Brooks, L.1
Lee, H.-S.2
-
15
-
-
0027576335
-
A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture
-
Apr
-
T. Kobayashi et al., "A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture", IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 523-527, Apr. 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, Issue.4
, pp. 523-527
-
-
Kobayashi, T.1
-
16
-
-
34547231313
-
A 10.6 mW/0.8 pJ power-scalable 1 GS/s 4b ADC in 0.18μm CMOS with 5.8 GHz ERBW
-
Jul
-
P. Nuzzo et al., "A 10.6 mW/0.8 pJ power-scalable 1 GS/s 4b ADC in 0.18μm CMOS with 5.8 GHz ERBW", in Proc. 43rd Design Automation Conf., Jul. 2006, pp. 873-878.
-
(2006)
Proc. 43rd Design Automation Conf
, pp. 873-878
-
-
Nuzzo, P.1
-
17
-
-
53849089244
-
Noise analysis of regenerative comparators for reconfigurable ADC architectures
-
Papers, Jul
-
P. Nuzzo et al., "Noise analysis of regenerative comparators for reconfigurable ADC architectures", IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 1441-1454, Jul. 2008.
-
(2008)
IEEE Trans. Circuits Syst. I, Reg
, vol.55
, Issue.6
, pp. 1441-1454
-
-
Nuzzo, P.1
-
18
-
-
34547357483
-
Efficient calibration through statistical behavioral modeling of a high-speed low-power ADC
-
Jun
-
P. Nuzzo et al., "Efficient calibration through statistical behavioral modeling of a high-speed low-power ADC", in Proc. PRIME, Jun. 2006, pp. 297-300.
-
(2006)
Proc. PRIME
, pp. 297-300
-
-
Nuzzo, P.1
-
19
-
-
49549085526
-
A 6b 0.2-to-0.9 V highly digital flash ADC with comparator redundancy
-
Feb
-
D. Daly and A. Chandrakasan, "A 6b 0.2-to-0.9 V highly digital flash ADC with comparator redundancy", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 554-555.
-
(2008)
IEEE ISSCC Dig. Tech. Papers
, pp. 554-555
-
-
Daly, D.1
Chandrakasan, A.2
-
20
-
-
39749142777
-
A signal-integrity self-test concept for debugging nanometer CMOS ICs
-
Feb
-
V. Petrescu et al., "A signal-integrity self-test concept for debugging nanometer CMOS ICs", in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 544-545.
-
(2006)
IEEE ISSCC Dig. Tech. Papers
, pp. 544-545
-
-
Petrescu, V.1
|