The analysis and improvement of a current-steering DACs dynamic SFDR - I: The cell-dependent delay differences

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 1, 2006, Pages 3-15

  Chen, Tao ^a   Gielen, Gielen G E ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Current steering digital to analog converters (DACs); Delay difference; Delay differences cancellation (DDC); Delay distribution; Spurious free dynamic range (SFDR); Switch and latch cell; Switching sequence

Indexed keywords

COMPUTER SIMULATION; DIGITAL TO ANALOG CONVERSION; FOURIER TRANSFORMS; MATHEMATICAL MODELS; SIGNAL DISTORTION;

CURRENT STEERING DIGITAL TO ANALOG CONVERTERS; DELAY DIFFERENCE; DELAY DIFFERENCE CANCELLATION; DELAY DISTRIBUTION; SPURIOUS FREE DYNAMIC RANGE (SFDR); SWITCHING SEQUENCE;

POWER CONVERTERS;

EID: 31444447742     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.854409     Document Type: Article

References (11)

1. 2 random walk CMOS DAC," IEEE J. Solid-State Circuits, vol. 34, pp. 1708-1718, Dec. 1999.
2. A. R. Bugeja and B. Song, "A self-trimming 14-b 100-MS/s CMOS DAC," IEEE J. Solid-State Circuits, vol. 35, pp. 1841-1852, 2000.
3. J. Hyde, T. Humes, C. Diorio, M. Thomas, and M. Figueroa, "A 300-ms/s 14-bit digital-to analog converter in logic CMOS," IEEE J. Solid-State Circuits, vol. 38, pp. 734-740, 2003.
4. A. Van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, "A 12 b 500 msample/s current-steering CMOS D/A converter," in Proc. IEEE 2001 ISSCC, vol. XLIV, Feb. 2001, pp. 366-367.
5. Y. Cong and R. Geiger, "A 1.5 v 14 b 100 MS/s self-calibrated DAC," in Proc. IEEE 2003 ISSCC, vol. 1, Feb. 2003, pp. 128-482.
6. A. Van den Bosch, M. Steyaert and W. Sansen, "SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters," in Proc. IEEE 1999 ISCAS, 1999, pp. 1193-1196.
7. S. Luschas and H. S. Lee, "Output impedance requirements for DAC's " in Proc. IEEE 2003 ISCAS, May 2003, pp. I-861-I-864.
8. T. Chen and G. Gielen, "Modeling of the impact of the current source output impedance on the SFDR of current-steering CMOS DA converters," in Proc. IEEE 2004 ISCAS, May 2004.
9. T. Chen and G. Gielen, "Analysis of the dynamic SFDR property of high-accuracy current-steering D/A converters," in Proc. IEEE 2003 ISCAS, May 2003, pp. I-973-I-976.
10. S. Haykin, An Introduction to Analog and Digital Communications. New York: Wiley, 1989.
11. Y. Cong and R. Geiger, "Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 7, pp. 585-595, Jul. 2000.