A statistical methodology for the design of high-performance CMOS current-steering digital-to-analog converters

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 4, 2002, Pages 377-394

  Crippa, Paolo ^a,b   Turchetti, Claudio ^a,b   Conti, Massimo ^a,b  

^a IEEE   (Italy)

^b UNIVERSITÀ POLITECNICA DELLE MARCHE   (Italy)

Author keywords

Behavioral modeling; CMOS; Current steering; Digital to analog converters; Mismatch; Statistical variations

Indexed keywords

STATISTICAL VARIATIONS;

COMPUTER SIMULATION; DIGITAL TO ANALOG CONVERSION; HARMONIC DISTORTION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MATRIX ALGEBRA; MOSFET DEVICES; RANDOM PROCESSES; SIGNAL TO NOISE RATIO; STATISTICAL METHODS;

CMOS INTEGRATED CIRCUITS;

EID: 0036539830     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.992761     Document Type: Article

References (29)

1. A 10-b 70-MS/s CMOS D/A converter
2. A 10-b 40 MHz 0.8-μm CMOS current-output D/A converter
3. A high yield 12-bit 250-MS/s CMOS A/D converter
4. 2
5. 2 random walk CMOS DAC
6. An accurate statistical yield model for CMOS current-steering D/A converters
7. Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter
8. Statistical design techniques for D/A converters
9. Verification of Nyquist data converters using behavioral simulation
10. Modeling of CMOS digital-to-analog converters for telecommunication
11. Statistical design of a D/A converter based on the current division technique
12. Influence of circuit imperfections on the performance of DAC's
13. Statistical behavioral modeling for A/D converters
14. Characterization and modeling of mismatch in MOS transistors for precision analog design
15. Matching properties of MOS transistors
16. Statistical modeling of device mismatch for analog MOS integrated circuits
17. Applying a submicron mismatch model to practical IC design
18. Parametric yield formulation of MOS IC's affected by mismatch effect
19. A flexible statistical model for CAD of submicrometer analog CMOS integrated circuits
20. Statistical modeling of MOS transistor mismatch based on the parameters' autocorrelation function
21. Overcoming insufficiencies of first order mismatch modeling
22. Mismatch modeling and simulation - A comprehensive approach
23. A statistical methodology for the design of high-performance current steering DAC's
24. Mismatch distance term compensation in centroid configurations with nonzero-area devices
25. Multi bit DAC with corrective gate to drain voltage for optimum matching under gradient temperature effects