A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 12, 1998, Pages 1871-1878

  Adams, Robert ^a,b,c,d,e   Nguyen, Khiem Q ^a,b,f,g   Sweetland, Karl ^b,h,i  

^a IEEE   (United States)

^b ANALOG DEVICES INC   (United States)

^c TUFTS UNIVERSITY   (United States)

^d DBX Inc   (United States)

^e Audio Engineering   (United Kingdom)

^f University of Toronto ^*

^g UNIVERSITY OF TORONTO   (Canada)

^h UNIVERSITY OF MASSACHUSETTS   (United States)

ⁱ RAYTHEON COMPANY   (United States)

Author keywords

Digital analog conversion; Sigma delta modulation

Indexed keywords

CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELTA SIGMA MODULATION; DIFFERENCE EQUATIONS; DIGITAL TO ANALOG CONVERSION; LOW PASS FILTERS; MODULATORS; OPERATIONAL AMPLIFIERS; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE;

ANALOG FILTER; DIGITAL TO ANALOG CONVERTER; NOISE SHAPED SCRAMBLING; SWITCHED CAPACITOR FILTER;

ELECTRIC CONVERTERS;

EID: 0032308948     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.735526     Document Type: Article

References (5)

1. T. Kwan, R. Adams, and R. Libert. "A stereo multi-bit sigma-delta D/A with asynchronous master-clock interface," in ISSCC Dig. Tech. Papers. Feb. 1996, pp. 226-227.
2. T. Kwan and R. Adams, "Data-directed scrambler for multi-bit noiseshaping D/A converters." U.S. Patent 5404 142.
3. Y. Matsuya, K. Uchimura, A. Iwata, and T. Kaneko, "A 17-bit ovenampling D-to-A conversion technology using multistage noise shaping," IEEE J. Solid State Ciruits, vol. 24, pp. 969-975, Aug. 1989.
4. T. Kwan, R. Adams, and R. Libert, "A stereo multi-bit sigma-delta D/A with asynchronous master-clock interface," IEEE J. Soild State Circuits, vol. 31, pp. 1881-1887, Dec. 1996.
5. L. R. Carley, "A noise shaping coder topology for 15+ bit converters," IEEE J. Solid State Circuits, vol. 24, pp. 267-273, Apr. 1989.