A continuous-time ADC/DSP/DAC system with no clock and with activity-dependent power dissipation

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 11, 2008, Pages 2472-2481

  Schell, Bob ^a,b   Tsividis, Yannis ^c  

^a Och Spine at New York Presbyterian Hospitals   (United States)

^b Conexant Systems Inc ^*  (United States)

^c Columbia University ^*  (United States)

Author keywords

Asynchronous processing; Continuous time digital filter; Continuous time digital signal processing; Delay element; Delta modulator

Indexed keywords

ASYNCHRONOUS PROCESSING; CONTINUOUS-TIME DIGITAL FILTER; CONTINUOUS-TIME DIGITAL SIGNAL PROCESSING; DELAY ELEMENT; DELTA MODULATOR;

ANALOG TO DIGITAL CONVERSION; BANDPASS FILTERS; CLOCKS; CONTINUOUS TIME SYSTEMS; DELTA MODULATION; DIGITAL ARITHMETIC; DIGITAL FILTERS; DIGITAL SIGNAL PROCESSING; ELECTRIC FILTERS; INTEGRATED CIRCUITS; MODULATION; MODULATORS; SIGNAL PROCESSING; WAVE FILTERS;

DIGITAL TO ANALOG CONVERSION;

EID: 56849098704     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2005456     Document Type: Article

References (20)

1. Y. Tsividis, "Digital signal processing in continuous time: a possibility for avoiding aliasing and reducing quantization error," in Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, Montreal, Canada, 2004, vol. II, pp. 589-592.
2. B. Schell and Y. Tsividis, "Continuous-time digital signal processing," in Proc. 2007 IEEE Int. Symp. Circuits and Systems (ISCAS'07), New Orleans, LA, May 2007, pp. 2232-2235.
3. Z. Zhao, V. Smolyakov, and A. Prodic, "Continuous-time digital signal processing based controller for high-frequency DC-DC converters," in Proc. IEEE Applied Power Electronics Conf., Anaheim, CA, Feb. 2007, pp. 882-886.
4. Y. Li, K. Shepard, and Y. Tsividis, "A continuous-time programmable digital FIR filter," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2512-2520, Nov. 2006.
5. H. Inose, T. Aoki, and K. Watanabe, "Asynchronous delta-modulation system," Electron. Lett., vol. 2, no. 3, pp. 95-96, Mar. 1966.
6. R. Steele, Delta Modulation Systems. New York: Wiley, 1975.
7. G. Lockhart, "Digital encoding and filtering using delta modulation," Radio Electron. Eng., vol. 42, no. 12, pp. 547-551, Dec. 1972.
8. N. Kouvaras, "Operations on delta-modulated signals and their applications in the realizations of digital filters," Radio Electron. Eng., vol. 48, no. 9, pp. 431-438, Sep. 1978.
9. S. Hauck, "Asynchronous design methodologies: an overview," Proc. IEEE, vol. 83, no. 1, pp. 69-93, Jan. 1995.
10. M. B. Josephs, S. M. Nowick, and C. H. van Berkel, "Modeling and design of asynchronous circuits," Proc. IEEE, vol. 87, no. 2, pp. 234-242, Feb. 1999.
11. T. H.-Y. Meng, R. Broderson, and D. G. Messerschmitt, "Asynchronous design for programmable digital signal processors," IEEE Trans. Signal Process., vol. 39, pp. 939-952, Apr. 1991.
12. E. Allier, G. Sicard, L. Fesquet, and M. Renaudin, "A new class of asynchronous A/D converters based on time quantization," in Proc. 9th IEEE Int. Symp. Asynchronous Circuits and Systems, Vancouver, Canada, May 2003, pp. 196-205.
13. J. Mark and T. Todd, "A nonuniform sampling approach to data compression," IEEE Trans. Commun., vol. COM-29, no. 1, pp. 24-32, Jan. 1981.
14. J. Foster and T.-K. Wang, "Speech coding using time code modulation," in Proc. IEEE SoutheasCon, Williamsburg, VA, 1991, vol. 2, pp. 861-863.
15. N. Sayiner, H. V. Sorensen, and T. R. Viswanathan, "A level-crossing sampling scheme for A/D conversion," IEEE Trans. Circuits Syst. II, vol. 43, no. 4, pp. 335-339, Apr. 1996.
16. M. Bazes, "Two novel fully complementary self-biased CMOS differential amplifiers," IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. 165-168, Feb. 1991.
17. B. Schell and Y. Tsividis, "A low power tunable delay element suitable for asynchronous delays of burst information," IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1227-1234, May 2008.
18. G. Kim, M. K. Kim, B. S. Chang, and W. Kim, "A low-voltage, low-power CMOS delay element," IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 966-971, Jul. 1996.
19. G. Taylor, S. Moore, S. Wilcox, and P. Robinson, "An on-chip dynamically recalibrated delay line for embedded self-timed systems," in IEEE Asynch. Symp., Eilat, Israel, Apr. 2000, pp. 45-51.
20. B. Schell and Y. Tsividis, "A clockless ADC/DSP/DAC system with activity-dependent power dissipation and no aliasing," in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, 2008, pp. 550-551.