메뉴 건너뛰기




Volumn 35, Issue 3, 2000, Pages 318-325

55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; ENERGY GAP; PIPELINE PROCESSING SYSTEMS;

EID: 0033872609     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.826813     Document Type: Article
Times cited : (213)

References (32)
  • 1
    • 0032664038 scopus 로고    scopus 로고
    • A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
    • May
    • A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May 1999.
    • (1999) IEEE J. Solid-state Circuits , vol.34 , pp. 599-606
    • Abo, A.M.1    Gray, P.R.2
  • 2
    • 0033149162 scopus 로고    scopus 로고
    • Analog circuit performance and process scaling
    • June
    • A.-J. Annema, "Analog circuit performance and process scaling," IEEE Trans. Circuits Syst. II, vol. 46, pp. 711-725, June 1999.
    • (1999) IEEE Trans. Circuits Syst. II , vol.46 , pp. 711-725
    • Annema, A.-J.1
  • 3
    • 0002665190 scopus 로고    scopus 로고
    • A 75 mW 10 b 20 MSample/s CMOS subranging ADC with 59 dB SNDR
    • Feb.
    • B. Brandt and J. Lutsky, "A 75 mW 10 b 20 MSample/s CMOS subranging ADC with 59 dB SNDR," in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 322-323.
    • (1999) ISSCC Dig. Tech. Papers , pp. 322-323
    • Brandt, B.1    Lutsky, J.2
  • 4
    • 0031710312 scopus 로고    scopus 로고
    • 8 b 75 MSample/s 70 mW parallel pipelined ADC incorporating double sampling
    • Feb.
    • W. Bright, "8 b 75 MSample/s 70 mW parallel pipelined ADC incorporating double sampling," in ISSCC Dig. Tech. Papers. Feb. 1998, pp. 146-147.
    • (1998) ISSCC Dig. Tech. Papers , pp. 146-147
    • Bright, W.1
  • 6
    • 0032136627 scopus 로고    scopus 로고
    • Design techniques for a low-power low-cost CMOS A/D converter
    • Aug.
    • D.-Y. Chang and S.-H. Lee, "Design techniques for a low-power low-cost CMOS A/D converter," IEEE J. Solid-State Circuits, vol. 33, pp. 1244-1248, Aug. 1998.
    • (1998) IEEE J. Solid-state Circuits , vol.33 , pp. 1244-1248
    • Chang, D.-Y.1    Lee, S.-H.2
  • 7
    • 0029269932 scopus 로고
    • A 10 b, 20 Msample/s, 35 mW pipeline A/D converter
    • Mar.
    • T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995.
    • (1995) IEEE J. Solid-state Circuits , vol.30 , pp. 166-172
    • Cho, T.B.1    Gray, P.R.2
  • 8
    • 0030106088 scopus 로고    scopus 로고
    • A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS
    • Mar.
    • D. W. Cline and P. R. Gray, "A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS,μ IEEE J. Solid-State Circuits, vol. 31, pp. 294-303, Mar. 1996.
    • (1996) IEEE J. Solid-state Circuits , vol.31 , pp. 294-303
    • Cline, D.W.1    Gray, P.R.2
  • 9
    • 0031706867 scopus 로고    scopus 로고
    • Analog background calibration of a 10 b 40 MSample/s parallel pipelined ADC
    • Feb.
    • K. Dyer, D. Fu, S. H. Lewis, and P. Hurst, μAnalog background calibration of a 10 b 40 MSample/s parallel pipelined ADC,μ in ISSCC Dig. Tech. Papers, Feb. 1998, pp. 142-143.
    • (1998) ISSCC Dig. Tech. Papers , pp. 142-143
    • Dyer, K.1    Fu, D.2    Lewis, S.H.3    Hurst, P.4
  • 11
    • 0031069003 scopus 로고    scopus 로고
    • A MOSFET-only, 10 b, 200 kSamples/s A/D converter capable of 12 b untrimmed linearity
    • Feb.
    • C. Hammerschmied and Q. Huang, μA MOSFET-only, 10 b, 200 kSamples/s A/D converter capable of 12 b untrimmed linearity,μ in ISSCC Dig. Tech. Papers. Feb. 1997, pp. 132-133.
    • (1997) ISSCC Dig. Tech. Papers , pp. 132-133
    • Hammerschmied, C.1    Huang, Q.2
  • 13
    • 0032316909 scopus 로고    scopus 로고
    • A continuously calibrated 12-b. 10-MS/s. 3.3-V A/D converter
    • Dec.
    • J. M. Ingino and B. A. Wooley, "A continuously calibrated 12-b. 10-MS/s. 3.3-V A/D converter," IEEE J. Solid-State Circuits, vol. 33, pp. 1920-1931, Dec. 1998.
    • (1998) IEEE J. Solid-state Circuits , vol.33 , pp. 1920-1931
    • Ingino, J.M.1    Wooley, B.A.2
  • 16
    • 0027887674 scopus 로고
    • A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC
    • Dec.
    • K. Kusumoto, A. Matsuzawa, and K. Murata, "A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC," IEEE J. Solid-State Circuits, vol. 28, pp. 1200-1206, Dec. 1993.
    • (1993) IEEE J. Solid-state Circuits , vol.28 , pp. 1200-1206
    • Kusumoto, K.1    Matsuzawa, A.2    Murata, K.3
  • 17
    • 0032626968 scopus 로고    scopus 로고
    • Power optimization for pipeline analog-to-digital converters
    • May
    • P. T. F. Kwok and H. C. Luong, "Power optimization for pipeline analog-to-digital converters," IEEE Trans. Circuits Syst. II, vol. 46, pp. 549-553, May 1999.
    • (1999) IEEE Trans. Circuits Syst. II , vol.46 , pp. 549-553
    • Kwok, P.T.F.1    Luong, H.C.2
  • 18
    • 0023599417 scopus 로고
    • A pipelined 5-Msample/s 9-bit analog-to-digital converter
    • Mar.
    • S. H. Lewis and P. R. Gray, "A pipelined 5-Msample/s 9-bit analog-to-digital converter." IEEE J. Solid-State Circuits, vol. SC-22, pp. 954-961, Mar. 1987.
    • (1987) Ieee J. Solid-state Circuits , vol.SC-22 , pp. 954-961
    • Lewis, S.H.1    Gray, P.R.2
  • 19
    • 0026836960 scopus 로고
    • A 10-b 20-Msample/s analog-to-digital converter
    • Mar.
    • S. H. Lewis, "A 10-b 20-Msample/s analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992.
    • (1992) IEEE J. Solid-state Circuits , vol.27 , pp. 351-358
    • Lewis, S.H.1
  • 20
    • 0026901915 scopus 로고
    • Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications
    • Aug.
    • _, "Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications," IEEE Trans. Circuits Syst. II. vol. 39, pp. 516-523, Aug. 1992.
    • (1992) IEEE Trans. Circuits Syst. II , vol.39 , pp. 516-523
  • 22
    • 0033364066 scopus 로고    scopus 로고
    • A 500 MSample/s 6-bit Nyquist rate ADC for disk drive read channel applications
    • July
    • I. Mehr and D. Dalton, "A 500 MSample/s 6-bit Nyquist rate ADC for disk drive read channel applications," IEEE J. Solid-State Circuits, vol. 34, pp. 912-920, July 1999.
    • (1999) IEEE J. Solid-state Circuits , vol.34 , pp. 912-920
    • Mehr, I.1    Dalton, D.2
  • 23
    • 0031102957 scopus 로고    scopus 로고
    • A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers
    • Mar.
    • K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, "A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers," IEEE J. Solid-State Circuits, vol. 32, pp. 312-320, Mar. 1997.
    • (1997) IEEE J. Solid-state Circuits , vol.32 , pp. 312-320
    • Nagaraj, K.1    Fetterman, H.S.2    Anidjar, J.3    Lewis, S.H.4    Renninger, R.G.5
  • 25
    • 0032308622 scopus 로고    scopus 로고
    • A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter
    • Dec.
    • I. E. Opris, L. D. Lewicki, and B. C. Wong, "A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 33, pp. 1898-1903, Dec. 1998.
    • (1998) IEEE J. Solid-state Circuits , vol.33 , pp. 1898-1903
    • Opris, I.E.1    Lewicki, L.D.2    Wong, B.C.3
  • 26
    • 56349170293 scopus 로고    scopus 로고
    • A 3.3 V 10b 25 MSample/s two-step ADC in 0.35 μm CMOS
    • Feb.
    • H. van der Ploeg and R. Remmers, "A 3.3 V 10b 25 MSample/s two-step ADC in 0.35 μm CMOS," in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 318-319.
    • (1999) ISSCC Dig. Tech. Papers , pp. 318-319
    • Van Der Ploeg, H.1    Remmers, R.2
  • 28
    • 0029703489 scopus 로고    scopus 로고
    • A 14-bit 10-MHz calibration-tree CMOS pipelined A/D converter
    • June
    • L. Singer and T. Brooks, "A 14-bit 10-MHz calibration-tree CMOS pipelined A/D converter," in Symp. VLSI Circuits Dig. Tech. Papers, June 1996, pp. 94-95.
    • (1996) Symp. VLSI Circuits Dig. Tech. Papers , pp. 94-95
    • Singer, L.1    Brooks, T.2
  • 30
    • 0024122159 scopus 로고
    • A pipelined 13-bit, 250-ks/s, 5 V analog-to-digital converter
    • Dec.
    • S. Sutarja and P. R. Gray, "A pipelined 13-bit, 250-ks/s, 5 V analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 23. pp. 1316-1323, Dec. 1988.
    • (1988) IEEE J. Solid-state Circuits , vol.23 , pp. 1316-1323
    • Sutarja, S.1    Gray, P.R.2
  • 31
    • 0031378861 scopus 로고    scopus 로고
    • A 12-b, 60-MSample/s cascaded folding and interpolating ADC
    • Dec.
    • P. Vorenkamp and R. Roovers, "A 12-b, 60-MSample/s cascaded folding and interpolating ADC," IEEE J. Solid-State Circuits, vol. 32, pp. 1876-1886, Dec. 1997.
    • (1997) IEEE J. Solid-state Circuits , vol.32 , pp. 1876-1886
    • Vorenkamp, P.1    Roovers, R.2
  • 32
    • 0027553563 scopus 로고
    • A 10-b 50-MHz pipelined CMOS A/D converter with S/H
    • Mar.
    • M. Yotsuyanagi, T. Etoh, and K. Hirata, "A 10-b 50-MHz pipelined CMOS A/D converter with S/H," IEEE J. Solid-State Circuits, vol. 28, pp. 292-300, Mar. 1993.
    • (1993) IEEE J. Solid-state Circuits , vol.28 , pp. 292-300
    • Yotsuyanagi, M.1    Etoh, T.2    Hirata, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.