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Volumn 43, Issue 7, 2008, Pages 1648-1656

40 MHz IF 1 MHz bandwidth two-path bandpass ΣΔ modulator with 72 dB DR consuming 16 mW

Author keywords

Analog digital conversion; CMOS integrated circuits; Sigma delta modulation

Indexed keywords

MODULATION;

EID: 46749123876     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.923728     Document Type: Conference Paper
Times cited : (27)

References (14)
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  • 9
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    • A 10.7 MHz self-calibrated switched-capacitor-based multibit second-order bandpass ΣΔ modulator with on-chip switched buffer
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    • V. Colonna, G. Gandolfi, F. Stefani, and A. Baschirotto, "A 10.7 MHz self-calibrated switched-capacitor-based multibit second-order bandpass ΣΔ modulator with on-chip switched buffer," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1341-1346, Aug. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.8 , pp. 1341-1346
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  • 10
    • 44849135518 scopus 로고    scopus 로고
    • Two-path bandpass ΣΔ modulator with 40 MHz IF 72 dB DR at 1 MHz bandwidth consuming 16 mW
    • I. Galdi, E. Bonizzoni, F. Maloberti, G. Manganaro, and P. Malcovati, "Two-path bandpass ΣΔ modulator with 40 MHz IF 72 dB DR at 1 MHz bandwidth consuming 16 mW," in Proc. ESSCIRC, 2007, pp. 248-251.
    • (2007) Proc. ESSCIRC , pp. 248-251
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  • 11
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  • 12
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    • V. S. L. Cheung and H. C. Luong, "A 3.3-V 240-MS/s CMOS bandpass ΣΔ modulator using a fast-settling double-sampling SC filter," in Symp. VLSI Circuits Dig. Tech. Papers, 2004, pp. 84-87.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.