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Volumn , Issue , 2011, Pages 470-471

A 4GHz CT ΔΣ ADC with 70dB DR and -74dBFS THD in 125MHz BW

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CONTINUOUS TIME SYSTEMS;

EID: 79955711114     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746401     Document Type: Conference Paper
Times cited : (50)

References (9)
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    • Mitteregger, G.1    Ebner, C.2    Mechnig, S.3
  • 2
    • 70349283738 scopus 로고    scopus 로고
    • A 0.13μm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based Integrator and Quantizer
    • Feb.
    • M. Park and M. Perrott, "A 0.13μm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based Integrator and Quantizer," ISSCC Dig. Tech. Papers, pp. 170-171, Feb., 2009.
    • (2009) ISSCC Dig. Tech. Papers , pp. 170-171
    • Park, M.1    Perrott, M.2
  • 3
    • 77952206117 scopus 로고    scopus 로고
    • A 16b 250MS/s IF-sampling Pipelined A/D Converter with Background Calibration
    • Feb.
    • A.M.A. Ali, A. Morgan, C. Dillon, et al., "A 16b 250MS/s IF-sampling Pipelined A/D Converter with Background Calibration," ISSCC Dig. Tech Papers, pp. 292-293, Feb., 2010.
    • (2010) ISSCC Dig. Tech Papers , pp. 292-293
    • Ali, A.M.A.1    Morgan, A.2    Dillon, C.3
  • 4
    • 66149160506 scopus 로고    scopus 로고
    • A 1 GHz Bandwidth Low-Pass ΣΔ ADC with 20-50 GHz Adjustable Sampling Rate
    • May
    • A. Hart and S.P. Voinigescu , "A 1 GHz Bandwidth Low-Pass ΣΔ ADC With 20-50 GHz Adjustable Sampling Rate," IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1401-1414, May, 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.5 , pp. 1401-1414
    • Hart, A.1    Voinigescu, S.P.2
  • 5
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    • Jun.
    • J. Silva, U.-K. Moon, J. Steensgaard, and G.C. Temes, "Wideband Low-Distortion ΔΣ ADC Topology," Electronic Letters, vol. 37, no. 12, pp. 737-738, Jun., 2001.
    • (2001) Electronic Letters , vol.37 , Issue.12 , pp. 737-738
    • Silva, J.1    Moon, U.-K.2    Steensgaard, J.3    Temes, G.C.4
  • 6
    • 0030685638 scopus 로고    scopus 로고
    • A Methodology for Designing Continuous-Time Sigma-Delta Modulators
    • Mar.
    • P. Benabes, M. Keramat, and R. Kielbasa, "A Methodology for Designing Continuous-Time Sigma-Delta Modulators," Proc. IEEE ED & TC., pp. 46-50, Mar., 1997.
    • (1997) Proc. IEEE ED & TC. , pp. 46-50
    • Benabes, P.1    Keramat, M.2    Kielbasa, R.3
  • 7
    • 54249147523 scopus 로고    scopus 로고
    • A 56 mW Continuous-Time Quadrature Cascaded ΣΔ Modulator with 77 dB DR in a Near Zero-IF 20 MHz Band
    • Dec.
    • L.J. Breems, R. Rutten, R.H.M. van Veldhoven, and G. van der Weide, "A 56 mW Continuous-Time Quadrature Cascaded ΣΔ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band," IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2696-2705, Dec., 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.12 , pp. 2696-2705
    • Breems, L.J.1    Rutten, R.2    Van Veldhoven, R.H.M.3    Van Der Weide, G.4
  • 8
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    • Schinkel, D.1    Mensink, E.2    Kiumperink, E.3
  • 9
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    • B. Nikolic, V.G. Oklobdzija, V. Stojanovic, et al., "Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876-884, Jun., 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.6 , pp. 876-884
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.