-
1
-
-
34548841783
-
A 14b 20mW 640MHz CMOS CT ΣΔ ADC with 20MHz Signal Bandwidth and 12b ENOB
-
Feb.
-
G. Mitteregger, C. Ebner, S. Mechnig, et al., "A 14b 20mW 640MHz CMOS CT ΣΔ ADC with 20MHz Signal Bandwidth and 12b ENOB," ISSCC Dig. Tech. Papers, pp. 62-63, Feb., 2006.
-
(2006)
ISSCC Dig. Tech. Papers
, pp. 62-63
-
-
Mitteregger, G.1
Ebner, C.2
Mechnig, S.3
-
2
-
-
70349283738
-
A 0.13μm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based Integrator and Quantizer
-
Feb.
-
M. Park and M. Perrott, "A 0.13μm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based Integrator and Quantizer," ISSCC Dig. Tech. Papers, pp. 170-171, Feb., 2009.
-
(2009)
ISSCC Dig. Tech. Papers
, pp. 170-171
-
-
Park, M.1
Perrott, M.2
-
3
-
-
77952206117
-
A 16b 250MS/s IF-sampling Pipelined A/D Converter with Background Calibration
-
Feb.
-
A.M.A. Ali, A. Morgan, C. Dillon, et al., "A 16b 250MS/s IF-sampling Pipelined A/D Converter with Background Calibration," ISSCC Dig. Tech Papers, pp. 292-293, Feb., 2010.
-
(2010)
ISSCC Dig. Tech Papers
, pp. 292-293
-
-
Ali, A.M.A.1
Morgan, A.2
Dillon, C.3
-
4
-
-
66149160506
-
A 1 GHz Bandwidth Low-Pass ΣΔ ADC with 20-50 GHz Adjustable Sampling Rate
-
May
-
A. Hart and S.P. Voinigescu , "A 1 GHz Bandwidth Low-Pass ΣΔ ADC With 20-50 GHz Adjustable Sampling Rate," IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1401-1414, May, 2009.
-
(2009)
IEEE J. Solid-State Circuits
, vol.44
, Issue.5
, pp. 1401-1414
-
-
Hart, A.1
Voinigescu, S.P.2
-
5
-
-
0035821957
-
Wideband Low-Distortion ΔΣ ADC Topology
-
Jun.
-
J. Silva, U.-K. Moon, J. Steensgaard, and G.C. Temes, "Wideband Low-Distortion ΔΣ ADC Topology," Electronic Letters, vol. 37, no. 12, pp. 737-738, Jun., 2001.
-
(2001)
Electronic Letters
, vol.37
, Issue.12
, pp. 737-738
-
-
Silva, J.1
Moon, U.-K.2
Steensgaard, J.3
Temes, G.C.4
-
6
-
-
0030685638
-
A Methodology for Designing Continuous-Time Sigma-Delta Modulators
-
Mar.
-
P. Benabes, M. Keramat, and R. Kielbasa, "A Methodology for Designing Continuous-Time Sigma-Delta Modulators," Proc. IEEE ED & TC., pp. 46-50, Mar., 1997.
-
(1997)
Proc. IEEE ED & TC.
, pp. 46-50
-
-
Benabes, P.1
Keramat, M.2
Kielbasa, R.3
-
7
-
-
54249147523
-
A 56 mW Continuous-Time Quadrature Cascaded ΣΔ Modulator with 77 dB DR in a Near Zero-IF 20 MHz Band
-
Dec.
-
L.J. Breems, R. Rutten, R.H.M. van Veldhoven, and G. van der Weide, "A 56 mW Continuous-Time Quadrature Cascaded ΣΔ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band," IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2696-2705, Dec., 2007.
-
(2007)
IEEE J. Solid-State Circuits
, vol.42
, Issue.12
, pp. 2696-2705
-
-
Breems, L.J.1
Rutten, R.2
Van Veldhoven, R.H.M.3
Van Der Weide, G.4
-
8
-
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34548852188
-
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time
-
Feb.
-
D. Schinkel, E. Mensink, E. Kiumperink, et al., "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time," ISSCC Dig. Tech, Papers, pp. 314-315, Feb., 2007.
-
(2007)
ISSCC Dig. Tech, Papers
, pp. 314-315
-
-
Schinkel, D.1
Mensink, E.2
Kiumperink, E.3
-
9
-
-
0342906692
-
Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements
-
Jun.
-
B. Nikolic, V.G. Oklobdzija, V. Stojanovic, et al., "Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876-884, Jun., 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.6
, pp. 876-884
-
-
Nikolic, B.1
Oklobdzija, V.G.2
Stojanovic, V.3
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