Digital background calibration for memory effects in pipelined analog-to-digital converters

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 3, 2006, Pages 511-525

  Keane, John P ^a,b   Hurst, Paul J ^a   Lewis, Stephen H ^a  

^a University of California Davis   (United States)

^b AGILENT TECHNOLOGIES   (United States)

Author keywords

Analog to digital converter (ADC); Calibration; Dielectric materials; Switched capacitor circuits

Indexed keywords

ALGORITHMS; CALIBRATION; CAPACITANCE; DIELECTRIC MATERIALS; OPERATIONAL AMPLIFIERS;

CALIBRATION ALGORITHMS; MEMORY ERRORS; SWITCHED CAPACITOR CIRCUITS;

ANALOG TO DIGITAL CONVERSION;

EID: 33645834775     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.858760     Document Type: Article

References (16)

1. S. H. Lewis and P. R. Gray, "A pipelined 5-Msample/s 9-bit analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 954-961, Dec. 1987.
2. J. Ming and S. H. Lewis, "An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration," IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1489-1497, 2001.
3. B. Murmann and B. E. Boser, "A 12 b 75 MS/s pipelined ADC using open-loop residue amplification," in Int. Solid-State Circuits Conf., Dig. Tech. Papers, San Francisco, CA, Feb. 2003, pp. 328-329.
4. C. Grace, P. J. Hurst, and S. H. Lewis, "A 12 b 80 MS/s pipelined ADC with bootstrapped digital calibration," in Int. Solid-State Circuits Conf., Dig. Tech. Papers, vol. 47, San Francisco, CA, Feb. 2004, pp. 460-461.
5. J. P. Keane, P. J. Hurst, and S. H. Lewis, "Backgound interstage gain calibration technique for pipelined ADCs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 1, pp. 32-43, Jan. 2005.
6. J. W. Fattaruso, M. de Wit, G. Warwar, K.-S. Tan, and R. K. Hester, "The effect of dielectric relaxation on charge-redistribution A/D converters," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1550-1561, Dec. 1990.
7. A. Zanchi, F. Tsay, and I. Papantonopoulos, "Impact of capacitor dielectric relaxation on a 14-bit 70-MS/s pipeline ADC in 3-V BiCMOS," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2077-2086, Dec. 2003.
8. H. Reisinger, G. Steinlesberger, S. Jakschik, M. Gutsche, T. Hecht, M. Leonhard, U. Schroder, H. Seidl, and D. Schumann, "A comparative study of dielectric relaxation losses in alternative dielectrics," in Int. Electron Devices Meeting Tech. Dig., Dec. 2001, pp. 267-270.
9. S. H. Lewis, H. S. Fetterman, G. F. Gross Jr., R. Ramachandran, and T. R. Viswanathan, "A 10-b 20-Msample/s analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351-358, Mar. 1992.
10. K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, "A 250-mW, 8-b, 52-Msampes/s parallel-pipelined A/D converter with reduced number of amplifiers," IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 312-320, Mar. 1997.
11. A. M. A. Ali, "Methods and structures that reduce memory effects in analog-to-digital converters," U.S. Patent 6 861 969, Mar. 1, 2005.
12. X. Wang, P. J. Hurst, and S. H. Lewis, "A 12-bit 20-MS/s pipelined ADC with nested digital background calibration," in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, 2003, pp. 409-412.
13. Y. Chiu, C. W. Tsang, B. Nikolic, and P. R. Gray, "Least mean square adaptive digital background calibration of pipelined analog-to-digital converters," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 38-46, 2004.
14. E. J. Siragusa and I. Galton, "Gain error correction technique for pipelined analogue-to-digital converters," Electron. Lett., vol. 36, no. 7, pp. 617-618, Mar. 2000.
15. H. S. Fetterman, D. G. Martin, and D. A. Rich, "CMOS pipelined ADC employing dither to improve linearity," in Proc. IEEE Custom Integrated Circuits Conf., San Diego, CA, May 1999, pp. 109-112.
16. I. Galton, "Digital cancellation of D/A converter noise in pipelined A/D converters," IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process., vol. 47, no. 3, pp. 185-196, Mar. 2000.