Digital synthesizers and transmitters for software radio

Digital Synthesizers and Transmitters for Software Radio

Volumn , Issue , 2005, Pages 1-359

  Vankka, Jouko ^a  

^a AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

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EID: 84895229406     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/1-4020-3195-5     Document Type: Book

References (604)

1. [Asb99] P. Asbeck, J. Mink, T. Itoh, and G. Haddad, "Device and Circuit Approaches for Next-Generation Wireless Communications, " Microwave J., Vol. 42, No. 2, pp. 22-42, Feb. 1999.
2. [Bat92] A. Bateman, "The Combined Analogue Locked Loop Universal Modulator (CALLUM), " In Proceedings of the 42nd IEEE Vehicular Technology Conference, May 1992, pp. 759-763.
3. [Bat98] A. Bateman, and C. K. Yuen, "Method and Apparatus for Amplifying, Modulating and Demodulating, " U. S. Patent 5, 719, 527, Feb. 17, 1998.
4. [Bax01] W. T. Bax, and M. A. Copeland, "A GMSK Modulator Using a σΔ Frequency Discriminator-based Synthesizer, " IEEE J. Solid-State Circuits, Vol. 36, No. 8, pp. 1218-1227, Aug. 2001.
5. [Bax99] W. T. Bax, "Modulation and Frequency Synthesis for Wireless Digital Radio, " PhD Thesis, Carleton University, October 1999.
6. [Cha95] K. Y. Chan, and A. Bateman, "Linear modulators Based on RF synthesis: Realization and Analysis, " IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, Vol. 42, No. 6, pp. 321-333, June 1995.
7. [Che68] E. M. Cherry, and D. E. Hooper, "Amplifying Devices and Low-Pass Amplifier Design, " John Wiley and Sons, Inc., New York, 1968.
8. [Chi35] H. Chireix, "High Power Outphasing Modulation, " Proceedings IRE, Vol. 23, No. 11, Nov. 1935, pp. 1370-1392.
9. [Cox74] D. C. Cox, "Linear Amplification with Nonlinear Components, " IEEE Trans. Commun., Vol. COM-22, pp. 1942-1945, Dec. 1974.
10. [Cox75a] D. C. Cox, "Linear Amplification by Sampling Techniques: A New Application for Delta Coders, " IEEE Trans. on Comm., Vol. 23, No. 8, pp. 793-798, Aug. 1975.
11. [Cox75b] D. C. Cox, and R. P. Leck, "Component Signal Separation and Recombination for Linear Amplification with Nonlinear Components, " IEEE Transactions on Communications, Vol. 23, pp. 1281-1287, Nov. 1975.
12. [Dar98] S. Ampem-Darko, and H. S. Al-Raweshidy, "Gain/Phase Imbalance Cancellation Technique in LINC Transmitters, " Electron. Lett., Vol. 34, No. 22, pp. 2093-2094, Oct. 1998.
13. [Das92] M. K. Dasilva, "Vector Locked Loop, " U. S. Patent 5, 105, 168, Apr. 14, 1992.
14. [Fen97] J. Fenk, "Highly Integrated RF-ICs for GSM and DECT, " IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 1997, pp. 69-72.
15. [Ger01] D. Gerna, A. Giry, D. Manstretta, D. Belot, and D. Pache, "1W 900 MHz Direct Conversion CMOS Transmitter for Paging Applications, " RFIC Symposium 2001 Digest of Technical Papers, pp. 191-194.
16. [Het91] S. A. Hetzel, A. Bateman, and J. P. McGeehan, "LINC Transmitter, " Electronics Letters, Vol. 27, No. 10, pp. 844-846, May 1991.
17. [Irv98] G. Irvine, and et al., "An Up-Conversion Loop Transmitter IC for Digital Mobile Telephones, " ISSCC Digest of Technical Papers, Feb. 1998, pp. 364-365.
18. [Iwa00] M. Iwamoto, A. Jayaraman, G. Hanington, P. F. Chen, A. Bellora, W. Thornton, L. E. Larson, and P. M. Asbeck, "Bandpass Delta-Sigma Class-S Amplifier, " Electronics Letters, Vol. 36, 12, pp. 1010-1012, June 2000.
19. [Jay98] A. Jayaraman, P. F. Chen, G. Hanington, L. Larson, and P. Asbeck, "Linear High-Efficiency Microwave Power Amplifiers Using Bandpass Delta-Sigma Modulators, " IEEE Microwave and Guided Wave Letters, Vol. 8, 3, pp. 121-123, March 1998.
20. [Jen98] D. J. Jennings, and J. P. McGeehan, "Hardware Implementation of Optimal CALLUM Transmitter, " Electronics Letters, Vol. 34, No. 19, pp. 1816-1817, Sept. 1998.
21. [Jen99] D. J. Jennings, and J. P. McGeehan, "A High-Efficiency RF Transmitter Using VCO-Derived Synthesis: CALLUM, " IEEE Transactions on Microwave Theory and Techniques, Vol. 47, No. 6, June 1999, pp. 715-721.
22. [Kah52] L. R. Kahn, "Single-Sideband Transmission by Envelope Elimination and Restoration, " Proceedings IRE, Vol. 40, pp. 803-806, July 1952.
23. [Ken00] P. B. Kenington, "High-Linearity RF Amplifier Design, " Norwood, MA: Artech House, 2000.
24. [Key01] J. Keyzer, J. Hinrichs, A. Metzger, M. Iwamoto, I. Galton, and P. Asbeck, "Digital Generation of RF Signals for Wireless Communications with Band-Pass Delta-Sigma Modulation, " IEEE MTT-S Digest, pp. 2127-2130, 2001.
25. [Kob01] H. Kobayashi, J. M. Hinrichs, and P. M. Asbeck, "Current-Mode Class-D Power Amplifiers for High-Efficiency RF Applications, " IEEE Transactions on Microwave Theory and Techniques, Vol. 49, No. 12, pp. 2480-2485, Dec. 2001.
26. [Lee01] K-Y. Lee, S-W. Lee, Y. Koo, H-K. Huh, H-Y. Nam, J-W. Lee, J. Park, K. Lee, D-K. Jeong, and W. Kim, "Full-CMOS 2.4 GHz Wideband CDMA Transmitter and Receiver with Direct Conversion Mixers and DCOffset Cancellation, " Symposium on VLSI Circuits 2001 Digest of Technical Papers, pp. 7-10.
27. [Liu00] T-P. Liu, and E. Westerwick, "5-GHz CMOS Radio Tranceiver Front-End Chipset, " IEEE J. Solid-State Circuits, Vol. 35, pp. 1927-1933, Dec. 2000.
28. [McM02] D. R. McMahill, and C. G. Sodini, "A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK Automatically Calibrated σΔ Frequency Synthesizer, " IEEE J. Solid-State Circuits, Vol. 37, No. 1, pp. 18-26, Jan. 2002.
29. [Nag02] P. J. Nagle, D. P. Burton, E. P. Heaney, and F. J. McGrath, "A Wideband Linear Amplitude Modulator for Polar Transmitters Based on the Concept of Interleaving Delta Modulation, " ISSCC Digest of Technical Papers, Feb. 2002, pp. 296-297.
30. [Ors99] P. Orsatti, F. Piazza, and Q. Huang, "A 20-mA-Receive, 55-mATransmit, Single-Chip GSM Tranceiver in 0.25-um CMOS, " IEEE J. Solid-State Circuits, Vol. 34, pp. 1869-1880, Dec. 1999.
31. [Per97] M. H. Perrott, T. L. Tewksbury, and C. G. Sodini, "A 27-mW CMOS fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation, " IEEE J. Solid-State Circuits, Vol. 32, No. 12, pp. 2048-2060, Dec. 1997.
32. [Pet79] V. Petrovic, and W. Gosling, "Polar-loop Transmitter, " Electronics Letters, Vol. 15, No. 10, pp. 286-288, May 1979.
33. [Pet84] V. Petrovic, and C. N. Smith, "Reduction of Intermodulation Distortion by Means of Modulation Feedback, " In IEE Colloquium on Intermodulation-Causes, Effects and Mitigation, London, April 9, 1984, pp. 8/ 1-8.
34. [Raa85] F. H. Raab, "Efficiency of Outphasing RF Power-amplifier Systems, " IEEE Transactions on Communications, " Vol. 33, No. 10, pp. 1094-1099, Oct. 1985.
35. [Raa93] F. H. Raab, and D. J. Rupp, "HF Power Amplifier Operates in Both Class B and Class D, " in Proc. RF Expo West, San Jose, CA, Mar. 17-19, 1993, pp. 114-124.
36. [Raa96] F. H. Raab, "Intermodulation Distortion in Kahn-technique Transmitters, " IEEE Trans. On Microwave Theory and Techniques, Vol. 44, No. 12, December 1996, pp. 2273-2278.
37. [Raa98] F. H. Raab, and et al., "High Efficiency L-band Kahn-technique Transmitter, " Proc of IEEE MTT-S, Baltimore, USA, Vol. 2, June 1998, pp. 585-588.
38. [Raa99] F. H. Raab, "Drive Modulation in Kahn-technique Transmitters, " IEEE MTT-S Microwave Symposium Digest, 1999, Vol. 2, pp. 811-814.
39. [Raz98] B. Razavi, "RF Microelectronics, " Prentice-Hall PTR, New Jersey, USA, 1998.
40. [Ril94] T. Riley, and M. Copeland, "A Simplified Continuous Phase Modulator Technique, " IEEE Transactions on Circuits and Systems-II, Vol. 41, No. 5, May 1994, pp. 321-328.
41. [Rus76] A. J. Rustako, Jr., and Y. S. Yeh, "A Wide-Band Phase-Feedback Inverse-Sine Phase Modulator with Application Toward a LINC amplifier, " IEEE Transactions on Communications, Vol. 24, pp. 1139-1143, Oct. 1976.
42. [Shi00] B. Shi, and L. van Sundström, "A 200-MHz IF BiCMOS Signal Component Separator for Linear LINC Transmitters, " IEEE J. Solid-State Circuits, Vol. 35, pp. 987-993, July 2000.
43. [Som04] J. Sommarek, "Digital Modulators with On-Chip D/A Converters, " Licentiate's Thesis, Helsinki University of Technology, 2004.
44. [Spl01] A. Splett, and et al., "Solutions for Highly Integrated Future Generation Software Radio Basestation Transceivers, " in Proc. IEEE Custom Integrated Circuits Conf., 2001, pp. 511-518.
45. [Sta99] J. Staudinger, and et al., "800 MHz Power Amplifier Using Envelope Following Techniques, " Proc. of the IEEE Radio and Wireless Conference (RAWCON) 1999, Denver, Colorado, Aug. 1999, pp. 301-304.
46. [Su98] D. Su, and W. McFarland, "An IC for Linearizing RF Power Amplifiers Using Envelope Elimination and Restoration, " IEEE Journal of Solid-State Circuits, Vol. 33, No. 12, Dec. 1998, pp. 2252-2258.
47. [Sun00] L. Sundström, "Spectral Sensitivity of LINC Transmitters to Quadrature Modulator Misalignments, " IEEE Trans. Veh. Technol., Vol. 49, pp. 1474-1487, July 2000.
48. [Sun94] L. Sundström, and M. Johansson, "The Effect of Modulation Scheme on LINC Transmitter Power Efficiency, " Electronics Letters, Vol. 30, No. 20, pp. 1643-1645, Sept. 1994.
49. [Sun95a] L. Sundström, "Automatic Adjustment of Gain and Phase Imbalances in LINC Transmitters, " Electronics Letters, Vol. 31, No. 3, pp. 155-156, Feb. 1995.
50. [Sun95b] L. Sundström, "Effects of Reconstruction Filters and Sampling Rate for a Digital Signal Component Separator on LINC Transmitter Performance, " Electron. Lett., Vol. 31, No. 14, pp. 1124-1125, July 1995.
51. [Tom89] S. Tomisato, K. Chiba, and K. Murota, "Phase Error Free LINC Modulator, " Electronic Letters, Vol. 25, No. 9, pp. 576-577, Apr. 1989.
52. [Var03] J. Varona, A. A. Hamoui, and K. Martin, "A Low-Voltage Fully-Monolithic a-Based Class-D Audio Amplifier, " in Proc. ESSCIRC'03, Sept. 2003, pp. 545-548.
53. [Yam97] T. Yamawaki, and et al., "A 2.7-V GSM RF Transceiver IC, " IEEE J. Solid-State Circuits, Vol. 32, pp. 2089-2096, Dec. 1997.
54. [Zha00] X. Zhang, and L. E. Larson, "Gain and Phase Error Free LINC Transmitter, " IEEE Trans. Veh. Technol., Vol. 49, pp. 1986-1994, Sept. 2000.
55. [Zha01] X. Zhang, L. E. Larson, and P. M. Asbeck, "Calibration Scheme for LINC Transmitter, " Electron. Lett., Vol. 37, No. 5, pp. 317-318, Mar. 2001.
56. [And97] P. Andreani, and L. Sundstrom, "Chip for Wideband Digital Predistortion RF Power Amplifier Linearisation, " Electronics Letters, " Vol. 33, No. 11, pp. 925-926, May 1997.
57. [Bat88] A. Bateman, D. M. Haines, and R. J. Wilkinson, "Linear Tranceiver Architectures, " In Proceedings of the 38th IEEE Vehicular Technology Conference, May 1988, pp. 478-484.
58. [Bau93] R. M. Bauman, "Adaptive Feed-Forward System, " U. S. Patent 4, 389, 618, June 21, 1993.
59. [Big88] E. Biglieri, S. Barberis, and M. Catena, "Analysis and Compensation of Nonlinearities in Digital Transmission Systems, " IEEE J. Select. Areas Commun., Vol. 6, pp. 42-51, Jan. 1988.
60. [Bla28] H. S. Black, "Translating System, " U. S. Patent 1, 686, 792, Oct. 9, 1928.
61. [Bla37] H. S. Black, "Wave Translation System, " U. S. Patent 2, 102, 671, Dec. 21, 1937.
62. [Boy81] R. W. Boyd, and R. C. Davis, "Adaptive Predistortion Technique for Linearizing a Power Amplifier for Digital Data Systems, " U. S. Patent 4, 291, 277, Sept. 22, 1981.
63. [Bri93] M. A. Briffa, and M. Faulkner, "Dynamically Biased Cartesian Feedback Linearization, " In Proceedings of the 43th IEEE Vehicular Technology Conference, May 1993, pp. 672-675.
64. [Bro88] A. N. Brown, and V. Petrovic, "Phase Delay Compensation in HF Cartesian-Loop Transmitters, " In Fourth International Conference on HF Communication Systems and Techniques, London, April 1988, pp. 200-204.
65. [Cav90] J. K. Cavers, "A Linearizing Predistorter with Fast Adaptation, " IEEE Transactions on Vehicular Technology, Vol. 39, No. 4, Nov. 1990, pp 374-382.
66. [Cav95] J. K. Cavers, "Adaptation Behavior of a Feedforward Amplifier Linearizer, " IEEE Transactions on Vehicular Technology, Vol. 44, No. 1, pp. 31-39, Feb. 1995.
67. [Cav97] J. Cavers, "Optimum Indexing in Predistorting Amplifier Linearizers, " in Proc. of IEEE Vehicular Technology Conference, Phoenix, USA, May 1997, pp. 676-680.
68. [Cha91] R. H. Chapman, and W. J. Turney, "Feedforward Distortion Cancellation Circuit, " U. S. Patent 5, 051, 704, Sept. 24, 1991.
69. [Crip02] S. C. Cripps, "Advanced Techniques in RF Power Amplifier Design, " Norwood, MA: Artech House, 2002.
70. [Dix86] J. P. Dixon, "A Solid-State Amplifier with Feedforward Correction for Linear Single-Sideband Applications, " In Proceedings of IEEE International Conference on Communications, Toronto, June 22-25, 1986, pp. 728-732.
71. [Fau94] M. Faulkner, and M. Johansson, "Adaptive Linearization using Predistortion-Experimental Results, " IEEE Transactions on Vehicular Technology, Vol. 43, No. 2, pp. 323-332, May 1994.
72. [Gha93] M. Ghaderi, S. Kumar, and D. E. Dodds, "Fast Adaptive Predistortion Lineariser Using Polynomial Functions, " Electronics Letters, Vol. 29, No. 17, pp. 1526-1528, August 1993.
73. [Gha94] M. Ghaderi, S. Kumar, and D. E. Dodds, "Adaptive Predistortion Lineariser Using Polynomial Functions, " IEE Proceedings on Communication, Vol. 141, No. 2, pp. 49-55, Apr. 1994.
74. [Ham95] S.-A. El-Hamamsy, "Design of High-Efficiency RF Class-D Power Amplifier, " IEEE Transactions on Power Electronics, Vol. 9, No. 3, pp. 297-308, May 1995.
75. [Has01] J. Hassani, and M. Kamarei, "A Flexible Method of LUT Indexing in Digital Predistortion Linearization of RF Power Amplifiers, " in Proc of IEEE International Symposium on Circuits and Systems, Sydney, Australia, Jun. 2001, pp. 53-56.
76. [Hil92] D. Hilborn, S. P. Stapleton, and J. K. Cavers, "An Adaptive Direct Conversion Transmitter, " In Proceedings of the 42nd IEEE Vehicular Technology Conference, May 1992, pp. 764-767.
77. [Hil94] D. Hilborn, S. P. Stapleton, and J. K. Cavers, "An Adaptive Direct Conversion Transmitter, " IEEE Transactions on Vehicular Technology, Vol. 43, No. 2, pp. 223-233, May 1994.
78. [Joh91] M. Johansson, and T. Mattsson, "Linearized High-Efficiency Power Amplifier for PCN, " Electronics Letters, Vol. 27, No. 9, pp. 762-764, Apr. 1991.
79. [Joh93] M. Johansson, T. Mattsson, L. Sundström, and M. Faulkner, "Linearization of Multi-Carrier Power Amplifiers, " In Proceedings of the 43rd IEEE Vehicular Technology Conference, May 1993, pp. 684-687.
80. [Joh94] M. Johansson, and L. Sundström, "Linearisation of RF Multicarrier Amplifiers Using Cartesian Feedback, " Electronics Letters, Vol. 30, No. 14, pp. 1110-1112, July 1994.
81. [Joh95] M. Johansson, and M. Faulkner, "Linearization of Wideband RF Power Amplifiers, " In Proceedings of Nordic Radio Symposium, Apr. 24-27, 1995, pp. 259-264.
82. [Kan98] H. W. Kang, Y. S. Cho, and D. H. Youn, "Adaptive Precompensation of Wiener Systems, " IEEE Trans. Signal Processing, Vol. 46, No. 10, pp. 2825-2829, Oct. 1998.
83. [Ken00] P. B. Kenington, "High Linearity RF Amplifier Design, " Norwood, MA: Artech House, 2000.
84. [Ken01] P. Kenington, M. Cope, R. Bennett, and J. Bishop, "A GSM-EDGE High Power Amplifier Utilising Digital Linearisation, " in IEEE Microwave Symposium Digest, Phoenix, USA, May 2001, pp. 1517-1520.
85. [Ken91a] P. B. Kenington, R. J. Wilkinson, and J. D. Marvill, "Broadband Linear Amplifier Design for a PCN Base-Station, " In Proceedings of the 41st IEEE Vehicular Technology Conference, St. Louis, May 19-22, 1991, pp. 155-160.
86. [Ken91b] P. B. Kenington, R. J. Wilkinson, and J. D. Marvill, "A Multi-Carrier Amplifier for Future Mobile Communications Systems, " In Proceedings of the IEE 6th International Conference on Mobile Radio and Personal Communication, Warwick, Dec. 1991, pp. 151-156.
87. [Ken92] P. B. Kenington, "Efficiency of Feedforward Amplifiers, " IEE Proceedings-G, Vol. 139, No. 5, pp. 591-593, Oct. 1992.
88. [Ken94] P. B. Kenington, M. A. Beach, A. Bateman, and J. P. McGeehan, "Apparatus and Method for Reducing Distortion in Amplification, " U. S. Patent 5, 334, 946, Aug. 2, 1994.
89. [Kon93] K. Konstantinou, P. Gardner, and D. K. Paul, "Optimization Method for Feedforward Linearisation of Power Amplifiers, " Electronics Letters, Vol. 29, No. 18, pp. 1633-1635, Sept. 1993.
90. [Mad99] K. Madani, "Reducing the Intermodulation Distortion in Multi-Carrier Microwave Power Amplifiers, " IEEE EDMO 1999 Conference, pp. 153-157.
91. [Man94] A. Mansell, and A. Bateman, "Practical Implementation Issues for Adaptive Predistortion Transmitter Linearisation, " In IEE Colloquium on 'Linear RF Amplifiers and Transmitters', (Digest No:1994/089), pp. 5/1-7, Apr. 1994.
92. [Mey74] R. G. Meyer, R. Eschenbach, and W. M. Edgerley, Jr., "A Wideband Feed-Forward Amplifier, " IEEE Journal on Solid-State Circuits, Vol. 9, No. 6, pp. 422-428, Dec. 1974.
93. [Min90] M. Minowa, M. Onoda, E. Fukuda, and Y. Daido, "Backoff Improvement of an 800-MHz GaAs FET Amplifier Using an Adaptive Nonlinear Distortion Canceller, " In Proceedings of the 40th IEEE Vehicular Technology Conference, May 1990, pp. 542-546.
94. [Muh00] K. Muhonen, R. Krishnamoorthy, and M. Kahverad, "Look-up Table Techniques for Adaptive Digital Predistortion: A Development and Comparison, " IEEE Trans. Vehicular Technology, Vol. 49, pp. 1995-2002, Sep. 2000.
95. [Mye94] D. P. Myer, "A Multicarrier Feed-Forward Amplifier Design, " Microwave Journal, pp. 78-88, Oct. 1994.
96. [Nag89] Y. Nagata, "Linear Amplification Technique for Digital Mobile Communications, " In Proceedings of the 39th IEEE Vehicular Technology Conference, May 1989, pp. 159-164.
97. [Nam83] J. Namiki, "An Automatically Controlled Predistorter for Multilevel Quadrature Amplitude Modulation, " IEEE Trans. Commun., Vol. COM-31, No. 5, pp. 707-712, May 1983.
98. [Nan85] M. Nannicini, P. Magni, and F. Oggionni, "Temperature Controlled Predistortion Circuits for 64 QAM Microwave Power Amplifiers, " in IEEE Microwave Symposium Digest, Vol. 85, June 1985, pp. 99-102.
99. [Nar91] S. Narahashi, and T. Nojima, "Extremely Low-Distortion Multicarrier Amplifier Self-Adjusting Feed-Forward (SAFF) Amplifier, " In Proceedings of IEEE International Communication Conference, 1991, pp. 1485-1490.
100. [Noj84] T. Nojima, and Y. Okamoto, "Predistortion Nonlinear Compensator for Microwave SSB-AM System, " Electronics and Communications in Japan, Vol. 67-B, No. 5, pp. 57-66, 1984.
101. [Noj85] T. Nojima, and T. Konno, "Cuber Predistortion Linearizer for Relay Equipment in 800 MHz band Land Mobile Telephone System, " IEEE Transactions on Vehicular Technology, Vol. 34, No. 4, pp. 169-177, Nov. 1985.
102. [Noj85] T. Nojima, T. Murase, and N. Imai, "The Design of Predistortion Linearization Circuit for High-Level Modulation Radio Systems, " In Proceedings from IEEE Global Telecommunications Conference, GLOBECOM '85, Dec. 1985, pp. 1466-1471.
103. [Obe91] M. G. Obermann, and J. F. Long, "Feed Forward Distortion Minimization Circuit, " U. S. Patent 5, 077, 532, Dec. 31, 1991.
104. [Ohi92] Y. Ohishi, M. Minowa, E. Fukuda, and T. Takano, "Cartesian Feedback Amplifier with Soft Landing, " In Proceedings of the third IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, Oct. 1992, pp. 402-406.
105. [Olv85] T. E. Olver, "Adaptive Feedforward Cancellation Technique That is Effective in Reducing Amplifier Harmonic Distortion Products as well as Intermodulation Distortion Products, " U. S. Patent 4, 560, 945, Dec. 24, 1985.
106. [Par94] K. J. Parsons, and P. B. Kenington, "The Efficiency of a Feedforward Amplifier with Delay Loss, " IEEE Transactions on Vehicular Technology, Vol. 43, No. 2, pp. 407-412, May 1994.
107. [Pet83] V. Petrovic, "Reduction of Spurious Emission from Radio Transmitters by Means of Modulation Feedback, " In IEE Conference on Radio Spectrum Conservation Techniques, Sept. 1983, pp. 44-49.
108. [Pro80] A. Prochazka, and R. Neumann, "Design of Wideband Feedforward Distribution Amplifier, " IEEE Transactions on Cable Television, Vol. 5, No. 2, pp. 72-79, Apr. 1980.
109. [Sal81] A. Saleh, "Frequency-Independent and Frequency-Dependent Nonlinear Models of TWT Amplifiers, " IEEE Trans. Commun., Vol. COM-29, pp. 1715-1720, Nov. 1981.
110. [Sal83] A. Saleh, and J. Salz, "Adaptive Linearization of Power Amplifiers in Digital Radio Systems, " Bell Syst. Tech. J., Vol. BSTJ-62, pp. 1019-1033, Apr. 1983.
111. [Sat83] G. Satoh, and T. Mizuno, "Impact of a New TWTA Linearizer upon QPSK/TDMA Transmission Performance, " IEEE Journal on Selected Areas in Communications, Vol. 1, No. 1, pp. 39-45, Jan. 1983.
112. [Sch81] M. Schetzen, "Nonlinear System Modeling Based on the Wiener Theory, " Proc. IEEE, Vol. 69, pp. 1557-1573, Dec. 1981.
113. [Se71b] H. Seidel, "A Microwave Feed-Forward Experiment, " The Bell System Technical Journal, Vol. 50, No. 9, pp. 2879-2916, Nov. 1971.
114. [Sei71a] H. Seidel, "A Feedforward Experiment Applied to an L-4 Carrier System Amplifier, " IEEE Transactions on Communication Technology, Vol. 19, No. 3, pp. 320-325, June 1971.
115. [Set00] Y. Seto, S. Mizuta, K. Oosaki, and Y. Akaiwa, "An Adaptive Predistortion Method for Linear Power Amplifiers, " In Proceedings of the 51st IEEE Vehicular Technology Conference, May 2000, pp. 1889-1893.
116. [Smi98] A. M Smith, and J. K. Cavers, "A Wideband Architecture for Adaptive Feedforward Linearization, " In Proceedings of the 48th IEEE Vehicular Technology Conference, May 1998, Vol. 3, pp. 2488-2492.
117. [Sta91] S. P. Stapleton, and J. K. Cavers, "A New Technique for Adaptation of Linearizing Predistorters, " In Proceedings of the 41st IEEE Vehicular Technolgy Conference, May 1991, pp. 753-758.
118. [Sta92a] S. P. Stapleton, and F. C. Costescu, "An Adaptive Predistorter for a Power Amplifier Based on Adjacent Channel Emission, " IEEE Transactions on Vehicular Technology, Vol. 41, No. 1, pp. 49-56, Feb. 1992.
119. [Sta92b] S. P. Stapleton, and F. C. Costescu, "An Adaptive Predistortion System, " In Proceedings of the 42nd IEEE Vehicular Technology Conference, May 1992, pp. 690-693.
120. [Sta92c] S. P. Stapleton, G. S. Kandola, and J. K. Cavers, "Simulation and Analysis of an Adaptive Predistorter Utilizing a Complex Spectral Convolution, " IEEE Transactions on Vehicular Technology, Vol. 41, No. 4, pp. 387-394, Nov. 1992.
121. [Ste88] R. D. Stewart, and F. F. Tusubira, "Feedforward Linearisation of 950MHz Amplifiers, " IEE Proceedings, Vol. 135, Pt. H, No. 5, pp. 347-350, Oct. 1988.
122. [Sun95] L. Sundström, "Digital RF Power Amplifier Linearisers-Analysis and Design, " PhD Thesis, Lund University, Aug. 1995.
123. [Sun96] L. Sundström, M. Faulkner, and M. Johansson, "Quantization Analysis and Design of a Digital Predistortion Linearizer for RF Power Amplifiers, " IEEE Trans. Veh. Technol., Vol. 45, pp. 707-719, Nov. 1996.
124. [Van80] J. Vanderkooy, and S. P. Lipshitz, "Feedforward Error Correction in Power Amplifiers, " Journal of the Audio Engineering Society, Vol. 28, No. 1/ 2, pp. 2-16, Jan./ Feb. 1980.
125. [Vuo01] J. H. K. Vuolevi, T. Rahkonen, and J. P. A. Manninen, "Measurement Technique for Characterizing Memory Effects in RF Power Amplifiers, " IEEE Transactions on Vehicular Technology, Vol. 49, No. 8, pp. 1383-1389, Aug. 2001.
126. [Whi94] S. M. Whittle, "A Practical Cartesian Loop Transmitter for Narrowband Linear Modulation PMR Systems, " In IEE Colloquium on 'Linear RF Amplifiers and Transmitters', (Digest No:1994/089), pp. 2 /1-5, April 1994.
127. [Wil92a] R. J. Wilkinson, and P. B. Kenington, "Specification of Error Amplifiers for Use in Feedforward Transmitters, " IEE Proceedings-G, Vol. 139, No. 4, pp. 477-480, Aug. 1992.
128. [Wil92b] R. J. Wilkinson, P. B. Kenington, and J. D. Marvill, "Power Amplification Techniques for Linear TDMA Base Stations, " In Proceedings from IEEE Global Communications Conference, GLOBECOM '92, part 1 (of 3), Dec. 6-9, 1992, pp. 74-78.
129. [Wri92] A. S. Wright, and W. G. Durtler, "Experimental Performance of an Adaptive Digital Linearized Power Amplifier, " IEEE Transactions on Vehicular Technology, Vol. 41, No. 4, pp. 395-400, Nov. 1992.
130. [Aki00] N. Akira, and H. Oshiroda, "Wide Band IQ Splitter Device and Proofreading Method, " Japanese Patent 2000151731, April 30, 2000.
131. [Cav90] J. K. Cavers, "A Linearizing Predistorter with Fast Adaptation, " IEEE Transactions on Vehicular Technology, Vol. 39, No. 4, Nov. 1990, pp 374-382.
132. [Cav91] J. K. Cavers, and M. Liao, "Adaptive Compensation for Imbalance and Offset Losses in Direct Conversion Transceivers, " IEEE Vehicular Technology Conference, 1991, pp. 578-583.
133. [Cav93] J. K. Cavers, and M. Liao, "Adaptive Compensation Methods for Imbalance and Offset Losses in Direct Conversion Transceivers, " IEEE Transactions on Vehicular Technology, Vol. 42, No. 4, Nov. 1993, pp. 581-588.
134. [Cav97] J. K. Cavers, "New Methods for Adaptation of Quadrature Modulators and Demodulators in Amplifier Linearization Circuits, " IEEE Transactions on Vehicular Technology, Vol. 46, No. 3, Aug. 1997, pp. 707-716.
135. [Fau91] M. Faulkner, T. Mattsson, and W. Yates, "Automatic Adjustment of Quadrature Modulators, " Electronic Letters, Vol. 27, No. 3, pp. 214-216, Jan. 1991.
136. [Fau92] M. Faulkner, and M. Johansson, "Correction of Mixer Nonlinearity in Quadrature Modulators, " Electronic Letters, Vol. 28, No. 3, pp. 293-295, Jan. 1992.
137. [Ger92] K. Gerlach, "The Effect of I, Q Mismatch Errors on Adaptive Cancellation, " IEEE Transactions on Aerospace and Electronic Systems, Vol. 28, No. 3, July 1992, pp. 729-740.
138. [Ger97] K. Gerlach, and M. J. Steiner, "An Adaptive Matched Filter that Compensates for I, Q Mismatch Errors, " IEEE Transactions on Signal Processing, Vol. 45, No. 12, Dec. 1997, pp. 3104-3107.
139. [Gla98] J. P. F. Glas, "Digital I/Q Imbalance Compensation in a Low-IF Receiver, " IEEE Global Telecommunications Conference, Vol. 3, 1998, pp. 1461-1466.
140. [Hay91] S. J. Haykin, "Adaptive Filter Theory, " Englewood Cliffs, NJ: Prentice-Hall, 1991.
141. [Hid00] K. Hideaki, and N. Akira, "Wide Band IQ Splitting Apparatus and Calibration Method Therefor, " European Patent Application 0984288, March 8, 2000.
142. [Hil92] D. Hilborn, S. P. Stapleton, and J. K. Cavers, "An Adaptive Direct Conversion Transmitter, " IEEE Vehicular Technology Conference, Vol. 2, 1992, pp. 764-767.
143. [Hil94] D. S. Hilborn, S. P. Stapleton, and J. K. Cavers, "An Adaptive Direct Conversion Transmitter, " IEEE Transactions on Vehicular Technology, Vol. 43, No. 2, May 1994, pp. 223-233.
144. [Hir96] M. Hironobu, "IQ Automatic Adjustment Circuit, " Japanese Patent 8204771, Aug. 9, 1996.
145. [Jui94] N. Juichi, "PSK Modulation Signal Evaluation Device and IQ Origin Offset Detector for PSK Modulation Signal, " Japanese Patent 6224952, Aug. 12, 1994.
146. [Loh93] A. Lohtia, P. A. Goud, and C. G. Englefield, "Digital Technique for Compensating for Analog Quadrature Modulator/Demodulator Impairments, " IEEE Pacific Rim Conference on Communications Computers and Signal Processing, Vol. 2, 1993, pp. 447-450.
147. [Man99] H. Manabu, "Quadrature Modulation Circuit, " Japanese Patent 11017752, Jan. 22, 1999.
148. [Man96] A. R. Mansell, and A. Bateman, "Transmitter Linearization Using Composite Modulation Feedback, " Electronic Letters, Vol. 32, No. 23, Nov. 1996, pp. 2120-2121.
149. [Mar00] R. Marchesani, "Digital Precompensation of Imperfections in Quadrature Modulators, " IEEE Transactions on Communications, Vol. 48, No. 4, Apr. 2000, pp. 552-556.
150. [McV02] J. D. McVey, "Modulation System Having on-line IQ Calibration, " U. S. Patent 6, 421, 397, July 16, 2002.
151. [Pie01] B. Jean-Pierre, "A Method for Controlling the Transmitter Part of a Radio Transceiver and a Corresponding Radio Transceiver, " European Patent Application 1154580, Nov. 14, 2001.
152. [Pun00] K-.P Pun, J. E. Franca, and C. Azeredo-Leme, "Wideband Digital Correction of I and Q Mismatch in Quadrature Radio Receivers, " in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2000, pp. 661-664.
153. [Ris01] M. Rishi, and M. P. Stroet, "Quadrature Modulator with Set-and-Forget Carrier Leakage Compensation, " U. S. Patent 6, 169, 463, Jan. 2, 2001.
154. [Xav01] C. Jean-Xavier, and M. Rossano, "Quadrature Modulator Imbalance Estimator and Modulator Stage Using It, " U. S. Patent 6, 208, 698, Mar. 27, 2001.
155. [Ahm89] H. M. Ahmed, "Efficient Elementary Function Generation with Multipliers, " in Proc. 9th Symposium on Computer Arithmetic, Santa Monica, CA, USA, Sept. 1989, pp. 52-59.
156. [Bra81] A. L. Bramble, "Direct Digital Frequency Synthesis, " in Proc. 35th Annu. Frequency Contr. Symp., USERACOM (Ft. Monmouth, NJ), May 1981, pp. 406-414.
157. [Cro83] R. E. Crochiere, and L. R. Rabiner, "Multirate Digital Signal Processing, " Englewood Cliffs, NJ: Prentice-Hall, 1983.
158. [Cur01] F. Curticãpean, and J. Niittylahti, "An Improved Digital Quadrature Frequency Down-Converter Architecture, " Asilomar Conf. on Signals, Syst. and Comput., Nov. 2001, pp. II-1318-1321.
159. [Dar70] S. Darlington, "On Digital Single-Sideband Modulators, " IEEE Trans. Circuit Theory, Vol. 17, No. 3, pp. 409-414, Aug. 1970.
160. [Dut78] D. L. Duttweiler, and D. G. Messerschmitt, "Analysis of Digitally Generated Sinusoids with Application to A/D and D/A Converter Testing, " IEEE Trans. on Commun., Vol. COM-26, pp. 669-675, May 1978.
161. [Gol96] B. G. Goldberg, "Digital Techniques in Frequency Synthesis, " McGraw-Hill, 1996.
162. [Gor75] J. Gorski-Popiel, "Frequency-Synthesis: Techniques and Applications, " IEEE Press, New York, USA, 1975.
163. [Hog81] E. B. Hogenauer, "An Economical Class of Digital Filters for Decimation and Interpolation, " IEEE Trans. Acoust., Speech, Signal Process., Vol. ASSP-29, No. 2, pp. 155-162, Apr. 1981.
164. [McC88] E. W. McCune, Jr., "Number Controlled Modulated Oscillator, " U. S. Patent 4, 746, 880, May 24, 1988.
165. [Mey98] U. Meyer-Bäse, S. Wolf, and F. Taylor, "Accumulator- Synthesizer with Error-Compensation, " IEEE Trans. Circuits and Systems II, Vol. 45, No. 7, pp. 885-890, July 1998.
166. [Nak97] T. Nakagawa, and H. Nosaka, "A Direct Digital Synthesizer with Interpolation Circuits, " IEEE J. of Solid State Circuits, Vol. 32, No. 5, pp. 766-770, May 1997.
167. [Nic87] H. T. Nicholas, and H. Samueli, "An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation, " in Proc. 41st Annu. Frequency Contr. Symp., June 1987, pp. 495-502.
168. [Nie98] J. Nieznanski, "An Alternative Approach to the ROM-less Direct Digital Synthesis, " IEEE J. of Solid State Circuits, Vol. 33, No. 1, pp. 169-170, Jan. 1998.
169. [Nos01a] H. Nosaka, Y. Yamaguchi, and M. Muraguchi, "A Non-Binary Direct Digital Synthesizer with an Extended Phase Accumulator, " IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Vol. 48, pp. 293-298, Jan. 2001.
170. [Nos01b] H. Nosaka, Y. Yamaguchi, A. Yamagishi, H. Fukuyama, and M. Muraguchi, "A Low-Power Direct Digital Synthesizer Using a Self-Adjusting Phase-Interpolation Technique, " IEEE J. Solid-State Circuits, Vol. 36, No. 8, pp. 1281-1285, Aug. 2001.
171. [Nuy90] P. Nuytkens, and P. V. Broekhoven, "Digital Frequency Synthesizer, " U. S. Pat. 4, 933, 890, June 12, 1990.
172. [Rah01] T. Rahkonen, H. Eksymä, A. Mäntyniemi, and H. Repo, "A DDS Synthesizer with Digital Time Domain Interpolator, " Analog Integrated Circuits and Signal Processing, Vol. 27, No. 1-2, pp. 111-118, Apr. 2001.
173. [Ric01] R. Richter, and H. J Jentschel, "A Virtual Clock Enhancement Method for DDS Using an Analog Delay Line, " IEEE J. Solid-State Circuits, Vol. 36, No. 7, pp. 1158-1161, July 2001.
174. [Son03] Y. Song and B. Kim, "A 330-MHz 15-b Quadrature Digital Synthesizer/ Mixer in 0.25 μm CMOS, " in Proc. 29th European Solid-State Circuits Conference, Estoril, Portugal, Sept. 2003, pp. 513-516.
175. [Sta94] Stanford Telecom STEL-2173 Data Sheet, the DDS Handbook, Fourth Edition, and Triquint Semiconductor TQ6122 Data Sheet, TQS Digital Communications and Signal Processing, 1994.
176. [Tan95a] L. K. Tan, and H. Samueli, "A 200 MHz Quadrature Digital Synthesizer/ Mixer in 0.8 μm CMOS, " IEEE J. of Solid State Circuits, Vol. 30, No. 3, pp. 193-200, Mar. 1995.
177. [Tie71] J. Tierney, C. Rader, and B. Gold, "A Digital Frequency Synthesizer, " IEEE Trans. Audio and Electroacoust., Vol. AU-19, pp. 48-57, Mar. 1971.
178. [Tor03] A. Torosyan, D. Fu, and A. N. Willson, Jr., "A 300-MHz Quadrature Direct Digital Synthesizer/Mixer in 0.25μm CMOS, " IEEE J. of Solid State Circuits, Vol. 38, No. 6, pp. 875-887, June 2003.
179. [Web72] J. A. Webb, "Digital Signal Generator Synthesizer, " U. S. Patent 3, 654, 450, Apr. 4, 1972.
180. [Wen95] A. Wenzler, and E. Lüder, "New Structures for Complex Multipliers and their Noise Analysis, " in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 1995, pp. 1, 432-1, 435.
181. [Won91] B. C. Wong, and H. Samueli, "A 200-MHz All-Digital QAM Modulator and Demodulator in 1.2-μm CMOS for Digital Radio Applications, " IEEE J. Solid-State Circuits, Vol. 26, No. 12, pp. 1970-1979, Dec. 1991.
182. [Zav88a] R. J. Zavrel, Jr., "Digital Modulation Using the NCMO, " RF Design, pp. 27-32, Mar. 1988.
183. [Zav88b] R. Zavrel, and E. W. McCune, "Low Spurious Techniques & Measurements for DDS Systems, " in RF Expo East Proc., 1988, pp. 75-79.
184. [Abu86a] A. I. Abu-El-Haija, and M. M. Al-Ibrahim, "Digital Oscillator Having Low Sensitivity and Roundoff Errors, " IEEE Trans. on Aerospace and Electronic Systems, Vol. AES-22, No. 1, pp. 23-32, Jan. 1986.
185. [Abu86b] A. I. Abu-El-Haija, and M. M. Al-Ibrahim, "Improving Performance of Digital Sinusoidal Oscillators by Means of Error-Feedback Circuits, " IEEE Trans. Circuits Syst., Vol. CAS-33, pp. 373-380, Apr. 1986.
186. [Ali01] M. M. Al-Ibrahim, "A Multifrequency Range Digital Sinusoidal Oscillator with High Resolution and Uniform Frequency Spacing, " IEEE Trans. on Circuits and Systems II, Vol. 48, No. 9, pp. 872-876, Sept. 2001.
187. [Ali97] M. M. Al-Ibrahim and A. M. Al-Khateeb, "Digital Sinusoidal Oscillator with Low and Uniform Frequency Spacing, " IEE Proceedings on Circuits, Devices and Systems, Vol. 144, No. 3, pp. 185-189, June. 1997.
188. [Asg93] S. M. Asghar, and A. R. Linz, "Frequency Controlled Recursive Oscillator Having Sinusoidal Output, " U. S. Patent 5, 204, 624, Apr. 20, 1993.
189. [Fli92] N. J. Fliege, and J. Wintermantel, "Complex Digital Oscillators and FSK Modulators, " IEEE Trans. on Signal Processing, Vol. SP-40, No. 2, pp. 333-342, Feb. 1992.
190. [Fur75] K. Furuno, S. K. Mitra, K. Hirano, and Y. Ito, "Design of Digital Sinusoidal Oscillators with Absolute Periodicity, " IEEE Trans. on
191. [Gol69] B. Gold, and C. M. Rader, "Digital Processing of Signals, " New York: McGraw-Hill, 1969.
192. [Gor85] J. W. Gordon and J. O. Smith, "A Sine Generation Algorithm for VLSI Applications, " in Proc. 1985 International Computer Music Conference (ICMC), Vancouver, 1985, pp. 165-168.
193. [Gra98] E. Grayver, and B. Daneshrad, "Direct Digital Frequency Synthesis Using a Modified CORDIC, " Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Vol. 5, pp. 241-244, 1998.
194. [Har83] I. Hartimo, "Self-Sustained Stable Oscillations of Second Order Recursive Algorithms, " in Proc. IEEE Int. Conference on Acoustics, Speech, and Signal Processing, USA, Apr. 1983, pp. 635-638.
195. [Kro96] B. W. Kroeger, and J. S. Baird "Numerically Controlled Oscillator with Complex Expotential Outputs Using Recursion Technique, " U. S. Patent 5, 517, 535, May. 14, 1996.
196. [Pal00] K. I. Palomäki, J. Niittylahti, and V. Lehtinen, "A Pipelined Digital Frequency Synthesizer Based on Feedback, " Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, Vol. 2, Aug. 2000 pp. 814-817.
197. [Pal99] K. I. Palomäki, J. Niittylahti, and M. Renfors, "Numerical Sine and Cosine Synthesis Using a Complex Multiplier, " Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, Vol. 4, June 1999, pp. 356-359.
198. [Pre94] L. Presti, and G. Cardamone, "A Direct Digital Frequency Synthesizer Using an IIR Filter Implemented with a DSP Microprocessor, " IEEE Int. Conf. Acoustics, Speech, and Signal Processing (ICASSP), Vol. 3, pp. 201-204, 1994.
199. [Pro97] J. G. Proakis, D. G. Manolakis, "Digital Signal Processing, Principles, " Macmillan Publishing Company, 1998, pp. 365.
200. [Tur03] C. S. Turner, "Recursive Discrete-Time Sinusoidal Oscillators, " IEEE Signal Processing Magazine, Vol. 20, No. 3, pp. 103-111, May 2003.
201. [Ahm82] H. M. Ahmed, "Signal Processing Algorithms and Architectures, " Ph. D. dissertation, Department of Electrical Engineering, Stanford University, CA. Jun. 1982.
202. [Ahm89] H. M. Ahmed, "Efficient Elementary Function Generation with Multipliers, " in Proc. 9th Symposium on Computer Arithmetic, Santa Monica, CA, USA, Sept. 1989, pp. 52-59.
203. [Ahn98] Y. Ahn, and S. Nahm, "VLSI Design of a CORDIC-based Derotator, " in Proc. ISCAS'98, Vol. 2, June 1998, pp. 449-452.
204. [Bu88] J. Bu, E. F. Deprettere, and F. du Lange, "On the Optimization of Pipelined Silicon CORDIC Algorithm, " in Proc. European Signal Processing Conference (EUSIPCO), Sep. 1988, pp. 1, 227-1, 230.
205. [Cav88a] J. R. Cavallaro, and F. T. Luk, "Floating Point CORDIC for Matrix Computations, " in Proc. IEEE International Conference on Computer Design, Oct. 1988, pp. 40-42.
206. [Cav88b] J. R. Cavallaro, and F. T. Luk, "CORDIC Arithmetic for a SVD processor, " Journal of Parallel and Distributed Computing, Vol. 5, pp. 271-290, June 1988.
207. [Coc92] D. Cochran, "Algorithms and Accuracy in the HP-35, " Hewlett Packard Journal, pp. 10-11, Jun. 1992.
208. [Cur01] F. Curticãpean, and J. Niittylahti, "An Improved Digital Quadrature Frequency Down-Converter Architecture, " Asilomar Conf. on Signals, Syst. and Comput., Nov. 2001, pp. II-1318-1321.
209. [Dac98] M. Dachroth, B. Hoppe, H. Meuth, and U. W. Steiger, "High-Speed Architecture and Hardware Implementation of a 16-bit 100 MHz Numerically Controlled Oscillator, " in Proc. ESSCIRC'98, Sept. 1998, pp. 456-459.
210. [Daw96] H. Dawid, and H. Meyr, "The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations, " IEEE Trans. on Computers, Vol. 45, No. 3, pp. 307-318, Mar. 1996.
211. [Dup93] J. Duprat, and J. M. Muller, "The CORDIC Algorithm: New Results for Fast VLSI Implementation, " IEEE Trans. on Computers, Vol. 42, No. 2, pp. 168-178, Feb. 1993.
212. [Dur87] R. A. Duryea, and C. Pottle, "Finite Precision Arithmetic Units in Jacobi SVD Architectures, " School of Electrical Engineering, Cornell University, Ithacaa, NY, Technical Report EE-CEG-87-11, Mar. 1987.
213. [Erc88] M. D. Ercegovac, and T. Lang, "Implementation of Fast Angle Calculation and Rotation Using On-Line CORDIC, " in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), June 1988, pp. 2, 703-2, 706.
214. [Erc90] M. D. Ercegovac, and T. Lang, "Redundant and On-Line CORDIC Application to Matrix Triangularization and SVD, " IEEE Trans. on Computers, Vol. 38, No. 6, pp. 725-740, June 1990.
215. [Fre95] S. Freeman, and M. O'Donnell, "A Complex Arithmetic Digital Signal Processor Using Cordic Rotators, " in Proc. ICASSP-95, Vol. 5, pp. 3191-3194, May 1995.
216. [Hav80] G. L. Haviland, and A. A. Tuszynski, "A CORDIC Arithmetic Processor Chip, " IEEE Trans. on Computers, Vol. 29, No. 2, pp. 68-79, Feb. 1980.
217. [Hsi95] S. F. Hsiao, and J. M. Delosme, "Householder CORDIC Algorithms, " IEEE Trans. Comput., Vol. 44, No. 8, pp. 990-1001, Aug. 1995.
218. [Hu92a] Y. H. Hu, "The Quantization Effects of the CORDIC Algorithm, " IEEE Trans. Signal Processing, Vol. 40, No. 4, pp. 834-844, April 1992.
219. [Hu92b] H. Y. Hu, "CORDIC-Based VLSI Architectures for Digital Signal Processing, " IEEE Signal Processing Magazine, pp. 16-35, July 1992.
220. [Hwa03] D. D. Hwang, D. Fu, and A. N. Willson, Jr, "A 400-MHz Processor for the Conversion of Rectangular to Polar Coordinates in 0.25-μm CMOS, " IEEE J. Solid-State Circuits, Vol. 38, , No. 10, pp. 1771-1775, Oct. 2003.
221. [Jan02] I. Janiszewski, B. Hoppe, and H. Meuth, "Numerically Controlled Oscillators with Hybrid Function Generators, " IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Vol. 49, pp. 995-1004, July 2002.
222. [Kot93] K. Kota, and J. R. Cavallaro, "Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors, " IEEE Trans. Comput., Vol. 42, No. 7, pp. 769-779, July 1993.
223. [Kun90] H. Kunemund, S. Soldner, S. Wohlleben, and T. Noll, "CORDIC Processor with Carry Save Architecture, " in Proc. ESSCIRC'90, Sep. 1990, pp. 193-196.
224. [Lan88] A. A. de Lange, A. J. van der Hoeven, E. F. Deprettere, and J. Bu, "An Optimal Floating-Point Pipeline CMOS CORDIC Processor, " in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), June 1988, pp. 2, 043-2, 047.
225. [Lee89] J. Lee, and T. Lang, "On-Line CORDIC for Generalized Singular Value Decomposition, " SPIE High Speed Computing II Vol 1058, pp. 235-247, 1989.
226. [Lee92] J. Lee, and T. Lang, "Constant-Factor Redundant CORDIC for Angle Calculation and Rotation, " IEEE Trans. Comput., Vol. 41, No. 8, pp. 1016-1025, Aug. 1992.
227. [Lin90] H. X. Lin, and H. J. Sips, "On-Line CORDIC Algorithms, " IEEE Trans. on Computers, Vol. 38, No. 8, pp. 1, 038-1, 052, Aug. 1990.
228. [Mad99] A. Madisetti, A. Kwentus, and A. N. Wilson, Jr., "A 100-MHz, 16-b, Direct Digital Frequency Synthesizer with a 100-dBc Spurious-Free Dynamic Range, " IEEE J. of Solid State Circuits, Vol. 34, No. 8, pp. 1034-1044, Jan. 1999.
229. [Nol90] T. Noll, "Carry-Save Arithmetic for High-Speed Digital Signal Processing, " in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 2, May 1990, pp. 982-986.
230. [Nol91] T. Noll, "Carry-Save Architectures for High-Speed Digital Signal Processing, " Journal of VLSI Signal Processing, Vol. 3, pp. 121-140, June 1991.
231. [Not88] S. Note, J. van Meerbergen, Catthoor, and H. de Man, "Automated Synthesis of a High Speed CORDIC Algorithm with the Cathedral-III Compilation System, " in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), June 1988, pp. 581-584.
232. [Par93] B. Parhami, "On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems, " IEEE Trans. on Computers, Vol. 42, No. 3, pp. 379-384, Mar. 1993.
233. [Phi95] L. Philips, I. Bolsens, and H. D. Man, "A Programmable CDMA IF Transceiver ASIC for Wireless Communications, " in Proc. IEEE Custom Integrated Circuits Conf., 1995, pp. 307-310.
234. [Sar98] R. Sarmiento, and et al., "A CORDIC Processor for FFT Computation and Its Implementation Using Gallium Arsenide Technology, " IEEE Trans. on VLSI Systems, Vol. 6, No. 1, pp. 18-30, Mar. 1998.
235. [Sch86] G. Schmidt, D. Timmermann, J. F. Bohme, and H. Hahn, "Parameter Optimization of the CORDIC Algorithm and Implementation in a CMOS Chip, " in Proc. European Signal Processing Conference (EUSIPCO), Sep. 1986, pp. 1, 291-1, 222.
236. [Son03] Y. Song and B. Kim, "A 330-MHz 15-b Quadrature Digital Synthesizer/ Mixer in 0.25 μm CMOS, " in Proc. 29th European Solid-State Circuits Conference, Estoril, Portugal, Sept. 2003, pp. 513-516.
237. [Tak87] N. Takagi, T. Asada, and S. A. Yajima, "Hardware Algorithm for Computing Sine and Cosine using Redundant Binary Representation, " Systems and Computers in Japan, Vol. 18, No. 9, pp. 1-9, 1987.
238. [Tak91] N. Takagi, T. Asada, and S. A. Yajima, "Redundant CORDIC Methods with a Constant Scale Factor for a Sine and Cosine Computation, " IEEE Trans. on Computers, Vol. 40, No. 9, pp. 989-995, Sep. 1991.
239. [Tim89] D. Timmermann, H. Hahn, and B. Hosticka, "Modified CORDIC Algorithm with Reduced Iterations, " Electronics Letters, Vol. 25, No. 15, pp. 950-951, July 1989.
240. [Tim91] D. Timmermann, H. Hahn, B. J. Hostica, and B. Rix, "A New Addition Scheme and Fast Scaling Factor Compensation Methods for CORDIC Algorithms, " INTEGRATION, the VLSI Journal, Vol. 11, pp. 85-100, 1991.
241. [Tor03] A. Torosyan, D. Fu, and A. N. Willson, Jr., "A 300-MHz Quadrature Direct Digital Synthesizer/Mixer in 0.25μm CMOS, " IEEE J. of Solid State Circuits, Vol. 38, No. 6, pp. 875-887, June 2003.
242. [Vol59] J. E. Volder, "The CORDIC Trigonometric Computing Technique, " IRE Trans. on Electron. Comput., Vol. C-8, pp. 330-334, Sept. 1959.
243. [Wal71] J. S. Walther, "A Unified Algorithm for Elementary Functions, " in Proc. Spring Joint Computer Conference, May 1971, pp. 379-385.
244. [Wan97] S. Wang, V. Piuri, and E. E. Swartzlander, "Hybrid CORDIC Algorithms, " IEEE Trans. on Computers, Vol. 46, No. 11, pp. 1202-1207, Nov. 1997.
245. [Yos89] H. Yoshimura, T. Nakanishi, and H. Yamauchi, "A 50 MHz CMOS Geometrical Mapping Processor, " IEEE Trans. on Circuits and Systems, Vol. 36, No. 10, pp. 1, 360-1, 363, 1989.
246. [Ana99] Analog Devices, "A Technical Tutorial on Digital Signal Synthesis, " Application Note, 1999.
247. [Ben48]W. R. Bennett, "Spectra of Quantized Signals, " Bell Sys. Tech. J., Vol. 27, pp. 446-472, July 1948.
248. [Jen88a] Y. C. Jenq, "Digital Spectra of Nonuniformly Sampled Signals: Fundamentals and High-Speed Waveform Digitizers, " IEEE Trans. Inst. and Meas., Vol. 37, pp. 245-251, June 1988.
249. [Jen88b] Y. C. Jenq, "Digital Spectra of Nonuniformly Sampled Signals-Digital Look-Up Tunable Sinusoidal Oscillators, " IEEE Trans. on Inst. and Meas., Vol. 37, No. 3, pp. 358-362, Sept. 1988.
250. [Jen97] Y. C. Jenq, "Direct Digital Synthesizer with Jittered Clock, " IEEE Trans. on Instrumentation and Measurement, Vol. 46, No. 3, pp. 653-655, June 1997.
251. [Kro00] V. F. Kroupa, V. Cizek, J. Stursa, and H. Svandova, "Spurious Signals in Direct Digital Frequency Synthesizers due to the Phase Truncation, " IEEE Transactions on Ultrasonics Ferroelectrics and Frequency Control, Vol. 47, No. 5, pp. 1166-1172, Sept. 2000.
252. [Lee66] D. B. Leeson, "A Simple Model of Feedback Oscillator Noise Spectrum, " IEEE Proc., Vol. 54, pp. 329-330, Feb. 1966.
253. [Man87] V. Manassewitsch, "Frequency Synthesizers Theory and Design, " 3nd Edition, New York: Wiley, 1980.
254. [McC79] J. H. McClellan, and C. M. Rader, "Number Theory in Digital Signal Processing, " Englewood Cliffs, NJ: Prentice-Hall, 1979.
255. [Meh83] S. Mehrgardt, "Noise Spectra of Digital Sine-Generators Using the Table-Lookup Method, " IEEE Trans. Acoust., Speech, Signal Process., Vol. ASSP-33, No. 4, pp. 1037-1039, Aug. 1983.
256. [Nic87] H. T. Nicholas, and H. Samueli, "An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation, " in Proc. 41st Annu. Frequency Contr. Symp., June 1987, pp. 495-502.
257. [Qua90] Qualcomm, "Hybrid PLL/DDS Frequency Synthesiser, " AN2334-4, 1990.
258. [Roh83] U. L. Rohde, "Digital PLL Frequency Synthesizers Theory and Design, " Prentice-Hall Inc., 1983.
259. [Tie71] J. Tierney, C. Rader, and B. Gold "A Digital Frequency Synthesizer, " IEEE Trans. Audio and Electroacoust., Vol. AU-19, pp. 48-57, Mar. 1971.
260. [Tor01] A. Torosyan, and A. N. Willson, Jr., "Analysis of the Output Spectrum for Direct Digital Frequency Synthesizers in the Presence of Phase Truncation and Finite Arithmetic Precision, " Proceedings of the 2nd Interna-d tional Symposium on Image and Signal Processing and Analysis, 2001, pp. 458-463.
261. [Ble87] B. A. Blesser, and B. N. Locanthi, "The Application of Narrow-Band Dither Operating at the Nyquist Frequency in Digital Systems to Provide Improved Signal-to-Noise Ratio over Conventional Dithering, " J. Audio Eng. Soc., Vol. 35, pp. 446-454, June 1987.
262. [Can92] J. C. Candy, and G. C. Temes, "Oversampling Delta-Sigma Data Converters, " IEEE Press, New York, 1992
263. [Car87] L. R. Carley, "An Oversampling Analog-to-Digital Converter Topology for High-Resolution Signal Acquisition Systems, " IEEE Trans. Circuits and Syst., CAS-34, pp. 83-90, Jan. 1987.
264. [Con99] G. A. Constantinides, P. Y. K. Cheung, and W. Luk, "Truncation Noise in Fixed-Point SFGs [digital filters], " Electron. Lett., Vol. 35, No. 23, pp. 2012-2014, Nov. 1999.
265. [Fla93] M. J. Flanagan, and G. A. Zimmerman, "Spur-Reduced Digital Sinusoid Generation Using Higher-Order Phase Dithering, " Asilomar Conf. on Signals, Syst. and Comput., Nov. 1993, pp. 826-830.
266. [Fla95] M. J. Flanagan, and G. A. Zimmerman, "Spur-Reduced Digital Sinusoid Synthesis, " IEEE Trans. Commun., Vol. COM-43, pp. 2254-2262, July 1995.
267. [Fle98] FLEX 10K Embedded Programmable Logic Family Data Sheet, Altera Corp., San Jose, CA, Oct. 1998.
268. [Gra93] R. M. Gray, and T. G. Stockholm, "Dithered Quantizers, " IEEE Trans. Inform. Theory., Vol. 39, pp. 805-812, May 1993.
269. [Har95] F. Harris and B. McKnight, "Error Feedback Loop Linearizes Direct Digital Synthesizers, " in Proc. IEEE 29th Asilomar Conf. on Signals, Systems, and Computers, Pacific Grove, USA, 30 Oct.-2 Nov. 1995, pp. 98-102.
270. [Jas87] S. C. Jasper, "Frequency Resolution in a Digital Oscillator, " U. S. Pat. 4, 652, 832, Mar. 24, 1987.
271. [Ker90] R. J. Kerr, and L. A. Weaver, "Pseudorandom Dither for Frequency Synthesis Noise, " U. S. Pat. 4, 901, 265, Feb. 13, 1990.
272. [Kos01] M. Kosunen, J. Vankka, M. Waltari, and K. Halonen, "A Multicarrier QAM Modulator for WCDMA Base Station with on-chip D/A converter, " Proceedings of CICC 2001 Conference, May 6-9 2001, San Diego, USA, pp. 301-304.
273. [Laz94] G. Lazzari, F. Maloberti, G. Oliveri, and G. Torelli, "Sinewave Modulation for Data Communication by Direct Digital Synthesis and Sigma Delta Techniques, " European Trans. Telecommun. and Related Technologies, Vol. 5, pp. 689-695, Nov.-Dec. 1994.
274. [Lea91a] P. O' Leary, M. Pauritsch, F. Maloberti, and G. Raschetti, "An Oversampling-Based DTMF Generator, " IEEE Trans. Commun., Vol. COM-39, pp. 1189-1191, Aug. 1991.
275. [Lea91b] P. O' Leary, and F. Maloberti, "A Direct Digital Synthesizer with Improved Spectral Performance, " IEEE Trans. Commun., Vol. COM-39, pp. 1046-1048, July 1991.
276. [Lju87] L. Ljung, "System Identification: Theory for the User, " Englewood Cliffs, NJ: Prentice-Hall, 1987.
277. [Nic88] H. T. Nicholas, H. Samueli, and B. Kim, "The Optimization of Direct Digital Frequency Synthesizer in the Presence of Finite Word Length Effects Performance, " in Proc. 42nd Annu. Frequency Contr. Symp., June 1988, pp. 357-363.
278. [Qua91a] Qualcomm Q2334, Technical Data Sheet, June 1991.
279. [Rei91] V. S. Reinhardt, and et al., "Randomized Digital/Analog Converter Direct Digital Synthesiser, " U. S. Pat. 5, 014, 231, May 7, 1991.
280. [Rei93] V. S. Reinhardt, "Spur Reduction Techniques in Direct Digital Synthesizers, " in Proc. IEEE Int. Frequency Cont. Symp., June 1993, pp. 230-241.
281. [Twi94] E. R. Twitchell, and D. B. Talbot, "Apparatus for Reducing Spurious Frequency Components in the Output Signal of a Direct Digital Synthesizer, " U. S. Pat. 5, 291, 428, Mar. 1, 1994.
282. [Van01] J. Vankka, and K. Halonen, "Direct Digital Synthesizers: Theory, Design and Applications, " Kluwer Academic Publishers, 2001.
283. [Van97] J. Vankka, "A Direct Digital Synthesizer with a Tunable Error Feedback Structure, " IEEE Transactions on Communications, Vol. 45, pp. 416-420, April 1997.
284. [Van98] J. Vankka, M. Waltari, M. Kosunen, and K. Halonen, "Direct Digital Syntesizer with on-Chip D/A-converter, " IEEE Journal of Solid-State Circuits, Vol. 33, No. 2, pp. 218-227, Feb. 1998.
285. [Whe83] C. E. Wheatley, III, "Digital Frequency Synthesiser with Random Jittering for Reducing Discrete Spectral Spurs, " U. S. Pat. 4, 410, 954, Oct. 18, 1983.
286. [Wil91] M. P. Wilson, and T. C. Tozer "Spurious Reduction Techniques for Direct Digital Synthesis, " IEE Coll. Digest 1991/172 on Direct Digital Frequency Synthesis, Nov. 1991, pp. 4/1-4/5.
287. [Zim92] G. A. Zimmerman, and M. J. Flanagan, "Spur Reduced Numerically-Controlled Oscillator for Digital Receivers, " Asilomar Conf. on Signals, Syst. and Comput., Dec. 1992, pp. 517-520.
288. [Ait02] A. Gutierrez-Aitken et al., "Ultrahigh-speed Direct Digital Synthesizer Using InP DHBT Technology, " IEEE Journal of Solid State Circuits, Vol. 37, No. 9, pp. 1115-1119, Sept. 2002.
289. [Ana94] Analog Devices AD 9955 data sheet, Rev. 0, 1994, and AD9712A data sheet, Rev. 0, 1994.
290. [Bel00] A. Bellaouar, and et al., "Low-Power Direct Digital Frequency Synthesis for Wireless Communications, " IEEE J. Solid-State Circuits, Vol. 35, No. 3, pp. 385-390, Mar. 2000.
291. [Bje91] B. E. Bjerede, "Suppression of Spurious Frequency Components in Direct Digital Frequency Synthesizer, " U. S. Patent 5 073 869, Dec. 17, 1991.
292. [Car02] D. D. Caro, E. Napoli, and A. G. M. Strollo, "Direct Digital Frequency Synthesizers Using High-order Polynomial Approximation, " Proc. IEEE 2002 ISSCC, pp. 134-135, Feb. 2002.
293. [Che92] B. W. Cheney, D. C. Larson and A. M. Frisch, "Delay Equalization Emulation for High Speed Phase Modulated Direct Digital Synthesis, " U. S. Patent 5, 140, 540, Aug. 18, 1992.
294. [Cho88] J. Chow, F. F. Lee, P. M. Lau, C. G. Ekroot, and J. E. Hornung, "1.25 GHz 26-bit Pipelined Digital Accumulator, " 1988 GaAs IC Symp. Technical Digest, Nov. 1988, pp. 131-134.
295. [Chr95] W. A. Chren, Jr., "RNS-Based Enhancements for Direct Digital Frequency Synthesis, " IEEE Trans. Circuits Syst.-Analog and Digital Signal Processing, Vol. CAS-42, No. 8, pp. 516-524, Aug. 1995.
296. [Chu98] S. W. Chu, and et al., "Digital Phase to Digital Sine and Cosine Amplitude Translator, " U. S. Patent 5, 774, 082, June 30, 1998.
297. [Cur01a] F. Curticãpean, and J. Niittylahti, "A Hardware Efficient Direct Digital Frequency Synthesizer, " in Proc. IEEE Int. Conference on Electronics Circuits and Systems, Malta, Sept. 2001, pp. 51-54.
298. [Cur01b] F. Curticãpean, K. I. Palomäki, and J. Niittylahti, "Direct Digital Frequency Synthesiser with High Memory Compression Ratio, " Electronic Letters, Vol. 37, No. 21, pp. 1275-1277, Oct. 2001.
299. [Cur03] F. Curticãpean, K. I. Palomäki, and J. Niittylahti, "Quadrature Direct Digital Frequency Synthesizer Using an Angle Rotation Algorithm, " in Proc. IEEE Int. Symposium on Circuits and Systems, Thailand, May 2003, pp. 81-84.
300. [Edm98] A. Edman, A. Björklid, and I. Söderquist, "A 0.8 μm CMOS 350 MHz Quadrature Direct Digital Frequency Synthesizer with Integrated D/A Converters, " Symposium on VLSI Circuits 1998 Digest of Technical Papers, pp. 54-55.
301. [Ekr88] C. G. Ekroot, and S. I. Long, "A GaAs 4-b Adder-Accumulator Circuit for Direct Digital Synthesis, " IEEE J. Solid-State Circuits, Vol. 23, pp. 573-580, April 1988.
302. [Ell96] P. M. Elliott, "Numerically Controlled Oscillator for Generating a Digitally Represented Sine Wave Output Signal, " U. S. Patent 5, 521, 534, May 28, 1996.
303. [Elt02] A. M. Eltawil, and B. Daneshrad, "Piece-Wise Parabolic Interpolation for Direct Digital Frequency Synthesis, " Proceedings of the IEEE Custom Integrated Circuits Conference, Orlando, May 2002, pp. 401-404.
304. [Ert96] R. Ertl, and J. Baier, "Increasing the Frequency Resolution of NCOSystems Using a Circuit Based on a Digital Adder, " IEEE Trans. Circuits and Systems II, Vol. 43, No. 3, pp. 266-269, Mar. 1996.
305. [Fan01] L. Fanucci, R. Roncella, and R. Saletti, "A Sine Wave Digital Synthesizer Based on a Quadratic Approximation, " Proceedings of the IEEE International Frequency Control Symposium, 2001, pp. 806-810.
306. [Fre89] R. A. Freeman, "Digital Sine Conversion Circuit for Use in Direct Digital Synthesizers, " U. S. Patent 4, 809, 205, Feb. 28, 1989.
307. [Gar90] J. F. Garvey, and D. Babitch, "An Exact Spectral Analysis of a Number Controlled Oscillator Based Synthesizer, " in Proc. 44th Annu. Freq. Contr. Symp., May 1990, pp. 511-521.
308. [GEC93] GEC-Plessey Semiconductors, Data Sheet PDSP16350 I/Q Splitter/ NCO, Dec. 1993.
309. [Gie89] B. Giebel, J. Lutz, and P. L. O'Leary, "Digitally Controlled Oscillator, " IEEE J. Solid-State Circuits, Vol. 24, pp. 640-645, June 1989.
310. [Gol88] B. G. Goldberg, "Digital Frequency Synthesizer, " U. S. Patent 4, 752, 902, June 21, 1988.
311. [Gol90] B. G. Goldberg, "Digital Frequency Synthesizer Having Multiple Processing Paths, " U. S. Patent 4, 958, 310, Sep. 18, 1990.
312. [Gol96] B. G. Goldberg, "Digital Techniques in Frequency Synthesis, " McGraw-Hill, 1996.
313. [Gor75] J. Gorski-Popiel, "Frequency-Synthesis: Techniques and Applications, " IEEE Press, New York, USA, 1975.
314. [Har91] M. V. Harris, "A J-Band Spread-Spectrum Synthesiser Using a Combination of DDS and Phaselock Techniques, " IEE Coll. Digest 1991/172 on Direct Digital Frequency Synthesis, Nov. 1991, pp. 8/1-10.
315. [Has84] R. Hassun, and A. W. Kovalick, "Waveform Synthesis Using Multiplexed Parallel Synthesizers, " U. S. Patent 4, 454, 486, June 12, 1984.
316. [Jac73] L. B. Jackson, "Digital Frequency Synthesizer, " U. S. Patent 3, 735, 269, May 22, 1973.
317. [Jan02] I. Janiszewski, B. Hoppe, and H. Meuth, "Numerically Controlled Oscillators with Hybrid Function Generators, " IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Vol. 49, pp. 995-1004, July 2002.
318. [Jia02] J. Jiang, and E. K. F. Lee, "A Low-Power Segmented Nonlinear DAC-based Direct Digital Frequency Synthesizer, " IEEE J. Solid-State Circuits, Vol. 37, No. 10, pp. 1326-1330, Oct. 2002.
319. [Jou99] J. M. Jou, S. R. Kuang, and R. D. Chen, "Design of Low-Error Fixed-Width Multipliers for DSP Applications, " IEEE Trans. on Circuits and Systems, Vol. 46, pp. 836-842, June 1999.
320. [Ken93] G. W. Kent, and N.-H. Sheng, "A High Purity, High Speed Direct Digital Synthesizer, " Proceedings of the IEEE International Frequency Control Symposium, 1993, pp. 207-211.
321. [Kos99] M. Kosunen, J. Vankka, M. Waltari, L. Sumanen, K. Koli, and K. Halonen, "A CMOS Quadrature Baseband Frequency Synthesizer/ Modulator, " Analog Integrated Circuits and Signal Processing, Vol. 18, No. 1, pp. 55-67, Jan. 1999.
322. [Lan01] J. M. P. Langlois, and D. Al-Khalili, "ROM Size Reduction with Low Processing Cost for Direct Digital Frequency Synthesis, " Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, BC, Aug. 2001, pp. 287-290.
323. [Lan02a] J. M. P. Langlois, and D. Al Khalili, "Hardware Optimized Direct Digital Frequency Synthesizer Architecture with 60 dBc Spectral Purity, " Proc. of IEEE Symp. on Circuits and Systems (ISCAS 2002), Vol. 5, May 2002, pp. 361-364.
324. [Lan02b] J. M. P. Langlois, and D. Al Khalili, "A New Approach to the Design of Low-Power Direct Digital Frequency Synthesizers, " in Proc. of IEEE Int.Frequency Control Symp., May 2002, pp. 654-661.
325. [Lan03a] J. M. P. Langlois, and D. Al Khalili, "Piecewise Continuous Linear Interpolation of the Sine Function for Direct Digital Frequency Synthesis, " Proc. of 2003 IEEE Radio Freq. Integr. Cyrcuits Symp., 2003, pp. 579-582.
326. [Lan03b] J. M. P. Langlois, and D. Al Khalili, "Novel Approach to the Design of Direct Digital Frequency Synthesizers Based on Linear Interpolation, " IEEE Trans. on Circuits and System II: Analog and Digital Signal Processing, Vol. 50, No. 9, pp. 567-578, Sept. 2003.
327. [Lau92] L. K. Lau, R. Jain, H. Samueli, H. T. Nicholas III, and E. G. Cohen, "DDFSGEN: A Silicon Compiler for Direct Digital Frequency Synthesizers, " Journal of VLSI Signal Processing, Vol. 4, pp. 213-226, April 1992.
328. [Lia97] S. Liao, and L-G. Chen, "A Low-Power Low-Voltage Direct Digital Frequency Synthesizer, " in Proc. Int. Symp. on VLSI Technology, Systems, and Applications, Hsinchu, Taiwan, June 1997, pp. 265-269.
329. [Liu01] S. I. Liu, T. B. Yu, and H. W. Tsao, "Pipeline Direct Digital Frequency Synthesiser Using Decomposition Method, " IEE Proceedings Circuits, Devices and Systems, Vol. 148, No. 3, pp. 141-144, June 2001.
330. [Lu93] F. Lu, H. Samueli, J. Yuan, and C. Svensson, "A 700-MHz 24-b Pipelined Accumulator in 1.2 μm CMOS for Application as a Numerically Controlled Oscillator, " IEEE J. Solid-State Circuits, Vol. 26, pp. 878-885, Aug. 1993.
331. [Mad99] A. Madisetti, A. Kwentus, and A. N. Wilson, Jr., "A 100-MHz, 16-b, Direct Digital Frequency Synthesizer with a 100-dBc Spurious-Free Dynamic Range, " IEEE J. of Solid State Circuits, Vol. 34, No. 8, pp. 1034-1044, Jan. 1999.
332. [McC84] R. D. McCallister, and D. Shearer, III, "Numerically Controlled Oscillator Using Quadrant Replication and Function Decomposition, " U. S. Patent 4, 486, 846, Dec. 4, 1984.
333. [McC91b] E. W. McCune, Jr., "Variable Modulus Digital Synthesizer, " U. S. Patent 5, 053, 982, Oct. 1, 1991.
334. [McI94] J. A. McIntosh, and E. E. Swartzlander, "High-speed Cosine Generator, " Asilomar Conf. on Signals, Syst. and Comput., 1994, pp. 273-277.
335. [Mer02] E. Merlo, K. H. Baek, and M. J. Choe, "Split Accumulator with Phase Modulation for High Speed Low Power Direct Digital Synthesizers, " in Proc. 15th Annual IEEE International ASIC/SOC Conference, New-York, USA, Sept. 25-28 2002, pp. 97-101.
336. [Moh02] A. N. Mohieldin, A. A. Emira, and E. Sánchez-Sinencio, "A 100-MHz 8-mW ROM-less Quadrature Direct Digital Frequency Synthesizer, " IEEE Journal of Solid State Circuits, Vol. 37, No. 10, pp. 1235-1243, Oct. 2002.
337. [Mor99] S. Mortezapour, and E. K. F. Lee, "Design of Low-Power ROMLess Direct Digital Frequency Synthesizer Using Nonlinear Digital-to Analog Converter, " IEEE J. Solid-State Circuits, Vol. 34, No. 10, pp. 1350-1359, Oct. 1999.
338. [Nel65] J. A. Nelder, and R. Mead, "A Simplex Method for Function Minimization, " Computer Journal, Vol. 7, 1965, pp. 308-313.
339. [Nic88] H. T. Nicholas, H. Samueli, and B. Kim, "The Optimization of Direct Digital Frequency Synthesizer in the Presence of Finite Word Length Effects Performance, " in Proc. 42nd Annu. Frequency Contr. Symp., June 1988, pp. 357-363.
340. [Nic91] H. T. Nicholas, and H. Samueli, "A 150-MHz Direct Digital Frequency Synthesiser in 1.25-μm CMOS with-90-dBc Spurious Performance, " IEEE J. Solid-State Circuits, Vol. 26, pp. 1959-1969, Dec. 1991.
341. [Nos01a] H. Nosaka, Y. Yamaguchi, and M. Muraguchi, "A Non-Binary Direct Digital Synthesizer with an Extended Phase Accumulator, " IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Vol. 48, pp. 293-298, Jan. 2001.
342. [Pal00] K. I. Palomaki, and J. Niittylahti, "Direct Digital Frequency Synthesizer Architecture Based on Chebyshev Approximation, " in Proc. 34th Asilomar Conf. on Signals, Systems and Computers, 29 Oct.-1 Nov. 2000, Vol. 2, pp. 1639-1643.
343. [Pal03] K. I. Palomäki, and J. Niittylahti, "A Low-Power, Memoryless Direct Digital Frequency Synthesizer Architecture, " Proceedings of the IEEE International Symposium on Circuits and Systems, May 2003, pp. II-77-80.
344. [Par00] M. Park, K. Kim, and J. A. Lee, "CORDIC-Based Direct Digital Synthesizer: Comparison with a ROM-Based Architecture in FPGA Implementation, " IEICE Trans. Fundam., Vol. E83-A, No. 6 June 2000.
345. [Pii01] O. Piirainen, "Method of Generating Signal Amplitude Responsive to Desired Function, and Converter, " U. S. Patent 6, 173, 301, Jan. 9, 2001.
346. [Pre92] W. H. Press, S. A. Teukolsky, W. T. Vetterling, and B. P. Flannery, "Numerical Recipes in C, The Art of Scientific Computing, " Second Edition, Press Syndicate of the University of Cambridge, New York, NY, USA, 1992.
347. [Qua91a] Qualcomm Q2334, Technical Data Sheet, June 1991.
348. [Ray94] Raytheon Semiconductor Data Book, Data Sheet TMC2340, 1994.
349. [Rog96] R. Rogenmoser, and Q. Huang, "A 800-MHz 1-μm CMOS Pipelined 8-b Adder Using True Single-Phase Clocked Logic-Flip-Flops, " IEEE J. of Solid State Circuits, Vol. 31, No. 3, pp. 401-409, Mar. 1996.
350. [Rub89] P. W. Ruben, E. F. Heimbecher, II, and D. L. Dilley, "Reduced Size Phase-to-Amplitude Converter in a Numerically Controlled Oscillator, " U. S. Patent 4, 855, 946, Aug. 8, 1989.
351. [Sai02] M. M. El Said, and M. I. Elmasry, "An Improved ROM Compression Technique for Direct Digital Frequency Synthesizers, " Proceedings of the IEEE International Symposium on Circuits and Systems, Phoenix AZ, May 2002, pp. 437-440.
352. [Sch03] W. Schofield, D. Mercer, and L. St. Onge, "A 16b 400MS/s DAC with <-80dBc IMD to 300 MHz and <-160dBm/Hz Noise Power Spectral Density," ISSCC Digest of Technical Papers, February 2003, San Francisco, USA, pp. 126-127.
353. [Sch99] M. J. Schulte, J. E. Stine, and J. G. Jansen, "Reduced Power Dissipation Through Truncated Multiplication, " Proc. IEEE Workshop on Low-Power Design, 1999, pp. 61-69.
354. [Sha01] S. S. Shah, and S. Collins, "A 200 MHz Analogue-ROM Based Direct Digital Frequency Synthesizer with Amplitude Modulation, " Proceedings of the IEEE International Symposium on VLSI Technology, Systems and Applications, Hsinchu, Taiwan, April 2001, pp. 53-56.
355. [Sod00] A. M. Sodagar, and G. R. Lahiji, "Mapping from Phase to Sine-Amplitude in Direct Digital Frequency Synthesizers Using Parabolic Approximation, " IEEE Trans. Circuits Syst. II, Vol. 47, pp. 1452-1457, Dec. 2000.
356. [Sod01] A. M. Sodagar, and G. R. Lahiji, "A Pipeline ROM-Less Architecture for Sine-Output Direct Digital Frequency Synthesizers Using the Second-Order Parabolic Approximation, " IEEE Transactions on Circuit and Systems II, Vol. 48, No. 9, pp. 850-857, Sep. 2001.
357. [Str02] A. G. M. Strollo, E. Napoli, and D. De Caro, "Direct Digital Frequency Synthesizers Using First-Order Polynomial Chebyshev Approximation, " in Proc. of 28th European Solid-State Circuits Conf. (ESSCIRC 2002), Sept. 2002, pp. 527-530.
358. [Str03a] A. Strollo, D. De Caro, E. Napoli, and N. Petra, "Direct Digital Frequency Synthesis with Dual-Slope Approach, " in Proc. 29th European Solid-State Circuits Conference, Estoril, Portugal, Sept. 16-18 2003, pp. 397-400.
359. [Str03b] A. G. M. Strollo, and D. De Caro, "Direct Digital Frequency Synthesizers Exploiting Piecewise Linear Chebyshev Approximation, " Microelectronics Journal, Vol. 34, pp. 1099-1106, Nov. 2003.
360. [Sun84] D. A. Sunderland, R. A. Strauch, S.S. Wharfield, H. T. Peterson, and C. R. Cole, "CMOS/SOS Frequency Synthesizer LSI Circuit for Spread Spectrum Communications, " IEEE J. of Solid State Circuits, Vol. SC-19, pp. 497-505, Aug. 1984.
361. [Tan95a] L. K. Tan, and H. Samueli, "A 200 MHz Quadrature Digital Synthesizer/ Mixer in 0.8 μm CMOS, " IEEE J. of Solid State Circuits, Vol. 30, No. 3, pp. 193-200, Mar. 1995.
362. [Tan95b] L. K. Tan, E. W. Roth, G. E. Yee, and H. Samueli, "A 800 MHz Quadrature Digital Synthesizer with ECL-Compatible Output Drivers in 0.8 μm CMOS, " IEEE J. of Solid State Circuits, Vol. 30, No. 12, pp. 1463-1473, Dec. 1995.
363. [Tho92] M. Thompson, "Low-Latency, High-Speed Numerically Controlled Oscillator Using Progression-of-States Technique, " IEEE J. Solid-State Circuits, Vol. 27, pp. 113-117, Jan. 1992.
364. [Tie71] J. Tierney, C. Rader, and B. Gold, "A Digital Frequency Synthesizer, " IEEE Trans. Audio and Electroacoust., Vol. AU-19, pp. 48-57, Mar. 1971.
365. [Tor01] F. Cardells-Tormo, and J. Valls-Coquillat, "Optimisation of Direct Digital Frequency Synthesisers Based on CORDIC, " Electronic Letters, Vol. 37, No. 21, pp. 1278-1280, Oct. 2001.
366. [Uus01] R. Uusikartano, and J. Niittylahti, "A Periodical Frequency Synthesizer for a 2.4-GHz Fast Frequency Hopping Transceiver, " IEEE Trans. on Circuits and Systems Part II, Vol. 48, No. 10, pp. 912-918, Oct. 2001.
367. [Van04] J. Vankka, J. Lindeberg, and K. Halonen, "A Direct Digital Synthesizer with Tunable Delta Sigma Modulator, " Analog and Integrated Circuit and Signal Processing, Vol. 38, No. 1, pp. 7-15, Jan. 2004.
368. [Vol59] J. E. Volder, "The CORDIC Trigonometric Computing Technique, " IRE Trans. on Electron. Comput., Vol. C-8, pp. 330-334, Sept. 1959.
369. [Wea90a] L. A. Weaver, and R. J. Kerr, "High Resolution Phase To Sine Amplitude Conversion, " U. S. Patent 4, 905, 177, Feb. 27, 1990.
370. [Whi93] S. A. White, "A Simple High-Performance Sine/Cosine Reference Generator, " Asilomar Conf. on Signals, Syst. and Comput., Nov. 1993, pp. 612-616.
371. [Yam98] A. Yamagishi, M. Ishikawa, and T. Tsukahara, "A 2-V 2-GHz Low-Power Direct Digital Frequency Synthesizer Chip Set for Wireless Communication, " IEEE J. Solid-State Circuits, Vol. 33, No. 2, pp. 210-217, Feb. 1998.
372. [Yan01] B.-D. Yang, and et al., "A Direct Digital Frequency Using A New ROM Compression Method, " in Proc. ESSCIRC'01, Sept. 2001, pp. 288-291.
373. [Yan02] B.-D. Yang, L.-S. Kim, and H.-K. Yu, "A High Speed Direct Digital Frequency Synthesizer Using a Low Power Pipelined Parallel Accumulator, " Proceedings of the IEEE International Symposium on Circuits and Systems, May 2002, pp. IV-373-376.
374. [Yua89] J. Yuan, and C. Svensson, "High-Speed CMOS Circuit Technique, " IEEE J. of Solid State Circuits, Vol. 24, No. 1, pp. 62-70, Feb. 1989.
375. [Zve67] A. Zvever, "Handbook of Filter Synthesis, " John Wiley & Sons, New York, 1967.
376. [All87] P. Allen, and D. Holberg, "CMOS Analog Circuit Design, " Oxford University Press, 1987.
377. [Bal87] G. Baldwin, et al., "Electronic Sampler Switch, " U. S. Patent 4, 639, 619, Jan. 27, 1987.
378. [Bas91] C. Bastiaansen, D. Wouter, J. Groeneveld, H. Schouwenaars, and H. Termeer, "A 10-b 40 MHz 0.8-μm CMOS Current-Output D/A Converter, " IEEE Journal of Solid State Circuits, Vol. 26, No. 7, pp. 917-921, July 1991.
379. [Bas97] J. Bastos, M. Steyaert, A. Pergoot, and W. Sansen, "Influence of Die Attachment on MOS Transistor Matching, " IEEE Trans. Semiconduct. Manufact., Vol. 10, pp. 209-217, May 1997.
380. [Bas98] J. Bastos, A. Marques, M. Steyaert, and W. Sansen, "A 12-bit Intrinsic Accuracy High-Speed CMOS DAC, " IEEE J. Solid-State Circuits, Vol. 33, No. 12, pp. 1959-1969, Dec. 1998.
381. [Bav98] N. van Bavel, "A 325 MHz 3.3V 10-Bit CMOS D/A Converter Core With Novel Latching Driver Circuit, " Proceedings of the IEEE Custom Integrated Circuits Conference 1998, pp. 245-248.
382. [Bos01] A. van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, "A 10-bit 1G Samples Nyquist Current-Steering CMOS D/A Converter, " IEEE Journal of Solid State Circuits, Vol. 36, No. 3, pp. 315-324, Mar. 2001.
383. [Bos01a] A. Van den Bosch, M. Steyaert, and W. Sansen , "An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters, " Analog Integrated Circuits and Signal Processing, Vol. 29, No. 3, pp. 173-180, Dec. 2001.
384. [Bos98] A. van den Bosch, M. Borremans, J. Vandenbussche, G. Van der Plas, A. Marques, J. Bastos, M. Steyaert, G. Gielen, and W. Sansen, "A 12 bit 200MHz Low Glitch CMOS D/A Converter, " Proceedings of the IEEE Custom Integrated Circuits Conference 1998, pp. 249-252.
385. [Bos99] A. van den Bosch, M. Steyaert, and W. Sansen, "SFDR-Bandwidth Limitations for High Speed High Resolution Current Steering CMOS D/A Converters, " Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems 1999, Vol. 3, pp. 1193-1196.
386. [Bug00] A. Bugeja, and B.-S. Song, "A Self-Trimming 14-b 100-MS/s CMOS DAC, " IEEE Journal of Solid State Circuits, Vol. 35, No. 12, pp. 1841-1852, Dec. 2000.
387. [Bug99] A. R. Bugeja, B. S. Song, P. L. Rakers, and S. F. Gillig, "A 14-b, 100-MS/s CMOS DAC Designed for Spectral Performance, " IEEE J. Solid-State Circuits, Vol. 34, No. 12, pp. 1719-1732, Dec. 1999.
388. [Bur01] M. Burns, and G. Roberts, "An Introduction to Mixed-Signal IC Test and Measurement, " Oxford University Press, 2001.
389. [Chi86] K. Chi, C. Geisenhainer, M. Riley, R. Rose, P. Sturges, B. Sullivan, R.Watson, R. Woodside, and M. Wu, "A CMOS Triple 100-Mbit/s Video D/A Converter with Shift Register and Color Map, " IEEE Journal of Solid-State Circuits, Vol. SC-21, pp. 989-995, Dec. 1986.
390. [Chi94] S.-Y. Chi, and C.-Y. Wu, "A 10-b 125-MHz CMOS Digital-to-Analog Converter (DAC) with Threshold-Voltage Compensated Current Sources, " IEEE Journal of Solid State Circuits, Vol. 29, No. 11, pp. 1374-1380, Oct. 1994.
391. [Con00] Y. Cong, and R. Geiger, "Switching Sequence Optimization for Gradient Error Compensation in Thermometer-Decoded DAC Arrays, " IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 47, No. 7, pp. 585-595, July 2000.
392. [Con02] Y. Cong, and R. L. Geiger, "Formulation of INL and DNL Yield Estimation in Current-Steering D/A Converters, " in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2002, pp. III.149-III.152.
393. [Con03] Y. Cong, and R. Geiger, "A 1.5V 14b 100MS/s Self-Calibrated DAC, " Digest of Technical Papers of the IEEE International Solid-State Circuits Conference 2003, pp. 128-129.
394. [Cre89] A. Cremonesi, F. Maloberti, and G. Polito, "A 100-MHz CMOS DAC for Video-Graphic Systems, " IEEE Journal of Solid State Circuits, Vol. 24, No. 3, pp. 635-639, June 1989.
395. [Cro97] D. Crook, and E. Stroud, "Drive Circuit and Method for Controlling the Crosspoint Levels of a Differential CMOS Switch Drive Signal, " U. S. Patent 5, 703, 519, Dec. 30, 1997.
396. [Cro98] D.Crook, and R. Cushing, "Sources of Spurious in a DDS/DAC System, " RF Design, pp. 28-42, April 1998.
397. [Ded02] I. Dedic, "Switch Driver Circuitry Having First and Second Output Nodes with a Current-Voltage Converter Connected There Between Providing Current Paths of First and Second Directions There Between and Switching Circuitry Connected Therewith, " U. S. Patent 6, 340, 939, Jan. 22, 2002.
398. [Ded99] I. Dedic, "Differential Switching Circuitry, " U. S. Patent 6, 100, 830, Aug. 8, 2000.
399. [Dor01] K. Doris, D. Leenaerts, and A. van Roermund, "Time Non Linearities in D/A Converters, " Proceedings of the European Conference on Circuit Theory and Design, Vol. III, pp. 353-356, 2001.
400. [Dud97] F. Dudek, B. M. Al-Hashimi, and M. Moniri, "CMOS Equaliser for Compensating sinc(x) Distortion of Video D/A Converters, " Electron. Lett., Vol. 33, No. 19, pp. 1618-1619, Sep. 1997.
401. [Ess97] K. Essenwanger, "Digital-to-Analog Converted and Method that Set Waveform Rise and Fall Times to Produce an Analog Waveform that Approximates a Piecewise Linear Waveform to Reduce Spectral Distortion, " U. S. Patent 5, 663, 728, Sept. 2, 1997.
402. [Ess98] K. Essenwanger, "Slewer Fractional-Order-Hold: The Ideal DAC Response For Direct Digital Synthesis, " Proceedings of the IEEE International Frequency Control Symposium 1998, pp. 379-389.
403. [Fal99] K. Falakshahi, C.-K. Yang, and B. Wooley, "A 14-bit 10-Msamples/s D/A Converter Using Multibit Modulation, " IEEE Journal of Solid State Circuits, Vol. 34, No. 5, pp. 607-615, 1999.
404. [Ger97] J. Gersbach, "Self Calibrating Segmented Digital-to-Analog Converter, " U. S. Patent 5, 642, 116, " June 24, 1997.
405. [Gro89] D. W. J. Groeneveld, H. J. Schouwenaars, H. A. H. Termeer, and C. A. A. Bastiaansen, "A Self-Calibration Technique for Monolithic High-Resolution D/A Converters, " IEEE J. Solid-State Circuits, Vol. 24, No. 6, pp. 1517-1522, Dec. 1989.
406. [Gus00] M. Gustavsson, J. Wikner, and N. Tan, "CMOS Data Converters for Communications," Kluwer Academic Publishers, 2000.
407. [Han99] J. Hanna, "Circuit and Method for Calibrating a Digital-to-Analog Converter, " U. S. Patent 5, 955, 980, Sept. 21, 1999.
408. [Hen97] P. Hendriks, "Specifying Communications DACs, " IEEE Spectrum, Vol. 34, No. 7, pp. 58-69, July 1997.
409. [Her91] R. Herman, A. McKay, and A. Chao, "Synchronizing Switch Arrangement for a Digital-to-Analog Converter to Reduce in-Band Switching Transients, " U. S. Patent 5, 059, 977, Oct. 22, 1991.
410. [Hyd03] J. Hyde, T. Humes, C. Diorio, M. Thomas, and M. Figueroa, "A 300-MS/s 14-bit Digital-to-Analog Converter in Logic CMOS, " IEEE Journal of Solid State Circuits, Vol. 38, No. 5, pp. 734-740, May 2003.
411. [Kas95] K. Kasai, and K. Matsuo, "Differential Current Source Circuit in DAC of Current Driving Type, " U. S. Patent 5, 406, 135, Apr. 11, 1995.
412. [Kim98] J. Kim, and K. Yoon, "An 8-bit CMOS 3.3-V-65MHz Digital-to-Analog Converter with a Symmetric Two-Stage Current Cell Matrix Architecture, " IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 45, No. 12, pp. 1605-1609, Dec. 1998.
413. [Koh95] H. Kohno Y. Nakamura, A. Kondo, H. Amishiro, T. Miki, and K. Okada, "A 350-MS/s 8-bit CMOS D/A-Converter Using Delayed Driving Scheme, " Proceedings of the IEEE Custom Integrated Circuits Conference 1995, pp. 211-214.
414. [Kos03] M. Kosunen, J. Vankka, I. Teikari, and K. Halonen, "DNL and INL Yield Models for a Current-Steering D/A Converter, " in Proc. ISCAS'03, Vol. I, May 2003, pp. 969-972.
415. [Lak86] K. Lakshmikumar, and et al., "Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design, " IEEE Journal of Solid State Circuits, Vol. 21, pp. 1057-1066, Dec. 1986.
416. [Lak88] K. Lakshmikumar, and et al., "Reply to 'A Comment on: Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design, " IEEE Journal of Solid State Circuits, Vol. 23, p. 296, Feb. 1988.
417. [Lin98] C-H. Lin, and K. Bult, "A 10b 500MSample/s CMOS DAC in 0.6 mm2, " IEEE Journal of Solid State Circuits, Vol. 33, No. 12, pp. 1948-1958, Dec. 1998.
418. [Luh00] L. Luh, J. Choma Jr., and J. Draper, "A High-Speed Fully Differential Current Switch, " IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 47, No. 4, pp. 358-363, Apr. 2000.
419. [Mar98] A. Marques, J. Bastos, A. van den Bosch, J. Vandenbussche, M. Steyaert, and W. Sansen, "A 12b Accuracy 300MSample/s Update Rate CMOS DAC, " Digest of Technical Papers of the IEEE International Solid-State Circuits Conference 1998, pp. 216-217.
420. [McC75] J. McCreary, and P. Gray, "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part I, " IEEE Journal of Solid State Circuits, Vol. 10, No. 6, pp. 371-379, Dec. 1975.
421. [Mer00] D. Mercer, "Differential Current Switch, " U. S. Patent 6, 031, 477, Feb. 29, 2000.
422. [Mer93] D. Mercer, "Two Approaches to Increasing Spurious Free Dynamic Range In High Speed DACs, " Proceedings of the IEEE Bipolar Circuits and Technology Meeting 1993, pp. 80-83.
423. [Mer94] D. Mercer, "A 16-b D/A Converter with Increaced Spurious Free Dynamic Range, " IEEE Journal of Solid State Circuits, Vol. 29, No. 10, pp. 1180-1185, Oct. 1994.
424. [Mer97] D. Mercer, D. Reynolds, D. Robertson, and E. Stroud, "Skewless Differential Current Switch and DAC Employing the Same, " U. S. Patent 5, 689, 257, Nov. 18, 1997.
425. [Mik86] T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Asaka, and Y. Horiba, "An 80-MHz 8-bit CMOS D/A-Converter, " IEEE Journal of Solid State Circuits, Vol. 21, No. 6, pp. 983-988, Dec. 1986.
426. [Nak91] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, "A 10-bit 70 MS/s CMOS D/A converter, " IEEE J. Solid-State Circuits, Vol. 26, pp. 637-642, Apr. 1991.
427. [Ngu92] T. Nguyen, "Spike Current Reduction in CMOS Switch Drivers, " U. S. Patent 5, 089, 728, Feb. 18, 1992.
428. [Pel89] M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching Properties of MOS Transistors, " IEEE Journal of Solid State Circuits, Vol. 24, No. 5, pp. 1433-1440, Oct. 1989.
429. [Pla99] G. Van der Plas, J. Vandenbussche, W. Sansen, M. Steyaert, and G. Gielen, "A 14-bit Intrinsic Accuracy Q2 Random Walk CMOS DAC, " IEEE J. Solid-State Circuits, Vol. 34, No. 12, pp. 1708-1718, Dec. 1999.
430. [Rad00] R. Radke, and A. Eshraghi, "A 14-Bit Current Mode SD-DAC Based Upon Rotated Data Weighted Averaging, " IEEE Journal of Solid State Circuits, Vol. 35, No. 8, pp. 1074-1084, Aug. 2000.
431. [Raz95] B. Razavi, "Principles of Data Conversion System Design, " IEEE Press, 1995.
432. [Sam88] H. Samueli, "The Design of Multiplierless FIR Filters for Compensating D/A Converter Frequency Response Distortion, " IEEE Trans. Circuits and Syst., Vol. 35, No. 8, pp. 1064-1066, Aug. 1988.
433. [Sch03] W. Schofield, D. Mercer, and L. St. Onge, "A 16b 400MS/s DAC with-80dBc IMD to 300MHz and-160dBm/Hz Noise Power Spectral Density, " Digest of Technical Papers of the IEEE International Solid-State Circuits Conference 2003, pp. 126-127.
434. [Sch04] B. Schafferer, and R. Adams, "A 3V CMOS 400mW 14b 1.4GS/s DAC for Multi-Carrier Applications, " ISSCC Digest of Technical Papers, February 2004, San Francisco, USA, pp. 360-361.
435. [Sch88] H. Schouvenaars, D. Wouter, J. Groeneweld, and H. Termeer, "A Low-Power Stereo 16-bit CMOS D/A Converter for Digital Audio, " IEEE Journal of Solid State Circuits, Vol. 23, No. 6, pp. 1290-1297, Dec. 1988.
436. [Sch97] W. Schnaitter, "Switchable Current Source for Digital-to-Analog Converter (DAC), " U. S. Patent 5, 598, 095, Jan. 1997.
437. [Sed91] A. Sedra, and K. Smith, "Microelectronic Circuits, " 3rd edition, Saunders College Publishing, 1991.
438. [Tak91] H.Takakura, M. Yokoyama, and A. Yamaguchi, "A 10 bit 80MHz Glitchless CMOS D/A Converter, " Proceedings of the IEEE Custom Integrated Circuits Conference 1991, pp. 26.5/1-26.5/4.
439. [Tei02] I. Teikari, "High-speed Nyquist-rate D/A Converter for Telecommunications Applications, " Master thesis, Helsinki University of Technology, Electronic Circuit Design Laboratory, Oct. 2002.
440. [Tii01] M. Tiilikainen, "A 14-bit 1.8-V 20mW 1-mm2 CMOS DAC, " IEEE Journal of Solid State Circuits, Vol. 36, No. 7, pp. 1144-1147, July 2001.
441. [Van02] J. Vankka, J. Pyykönen, J. Sommarek, M. Honkanen, and Kari Halonen, "A Multicarrier GMSK Modulator with on-chip D/A converter for Base Station, " IEEE Journal of Solid-State Circuits, Vol. 37, No. 10, pp. 1226-1234, Oct. 2002.
442. [Vol02] A. Volk, "Method To Reduce Glitch Energy in Digital-to-Analog Converter, " U. S. Patent 6, 507, 295, Jan. 14, 2003.
443. [Wu95] T.-Y. Wu, C.-T. Jih, J.-C. Chen, and C.-Y. Wu, "A Low Glitch 10-bit 75-Hz CMOS Video D/A Converter, " IEEE Journal of Solid State Circuits, Vol. 30, No. 1, pp. 68-72, Jan. 1995.
444. [Xu99] Y. Xu, and H. Min, "A Low-Power Video 10-Bit CMOS D/A Converter Using Modifed Look-Ahead Circuit, " IEEE Transactions on Consumer Electronics, Vol. 45, No. 2, pp. 295-298, May 1999.
445. [Zho01] Y. Zhou, and J. Yuan, "An 8-Bit 100-MHz Low Glitch Interpolation DAC, " Proceedings of the 2001 IEEE International Symposium on Circuits and Systems, Vol. 4, pp. 116-119.
446. [Che82] P. R. Chevillat, and G. Ungerboeck, "Optimum FIR Transmitter and Receiver Filters for Data Transmission over Band-Limited Channels, " IEEE Trans. Commun., Vol. 30, No. 8, pp. 1909-1915, Aug. 1982.
447. [Che99] C. Chen, and A. Willson, "A Trellis Search Algorithm for the Design of FIR Filters with Signed-Powers-of-Two Coefficients, " IEEE Transactions on Circuits and Systems-II, Vol. 46, No. 1, pp. 29-39, Jan. 1999.
448. [Con99] G. A. Constantinides, P. Y. K. Cheung, and W. Luk, "Truncation noise in Fixed-Point SFGs [digital filters], " Electron. Lett., Vol. 35, No. 23, pp. 2012-2014, Nov. 1999.
449. [Dua00] J. N. Duan, L. Ko, and B. Daneshrad, "A Highly Versatile Beamforming ASIC for Application in Broad-Band Fixed Wireless Access Systems, " IEEE J. of Solid State Circuits, Vol. 35, No. 3, pp. 391-400, Mar. 2000.
450. [Fli94] N. J. Fliege, "Multirate Digital Signal Processing, " John Wiley & Sons, 1994.
451. [Gra01] E. Grayver, and B. Daneshrad, "VLSI implementation of a 100-μW Multirate FSK Receiver, " IEEE J. of Solid State Circuits, Vol. 36, No. 11, pp. 1821-1828, Nov. 2001.
452. [Har96] R. Hartley, "Subexpression Sharing in Filters Using Canonic Signed Digit Multipliers, " IEEE Transactions on Circuits and Systems-II, Vol. 43, No. 10, pp. 677-688, Oct. 1996.
453. [Hat01] M. Hatamian, "Efficient FIR Filter for High-Speed Communication, " U. S. Patent 6, 272, 173, Aug. 7, 2001.
454. [Hau93] J. C. Hausman, R. R. Harnden, E. G. Cohen, and H. G. Mills, "Programmable Canonic Signed Digit Filter Chip, " U. S. Patent 5, 262, 974, Nov. 16, 1993.
455. [Haw96] R. Hawley, B. Wong, T. Lin, J. Laskowski, and H. Samueli, "Design Techniques for Silicon Compiler Implementations of High-Speed FIR Digital Filters, " IEEE Journal of Solid-State Circuits, Vol. 31, No. 5, pp. 656-667, May 1996.
456. [Hog81] E. B. Hogenauer, "An Economial Class of Digital Filters for Decimation and Interpolation, " IEEE Trans. Acoust., Speech, Signal Process., Vol. ASSP-29, No. 2, pp. 155-162, Apr. 1981.
457. [Hwa75] S. Hwang, "On Monotonicity of Lp and lp Norms, " IEEE Transactions on Acoustics, Speech, and Signal Processing, Dec. 1975, pp. 593-594.
458. [Jia97] Z. Jiang, and A. Willson, "Efficient Digital Filtering Architectures Using Pipelining/Interleaving, " IEEE Transactions on Circuits and Systems-II, Vol. 44, No. 2, pp. 110-119, Feb. 1997.
459. [Kho01] K. Y. Khoo, Z. Yu, and A. Willson, "Design of Optimal Hybrid Form FIR Filter, " IEEE International Symposium on Circuits and Systems 2001, Vol. 2, pp. 621-624.
460. [Kho96] K. Y. Khoo, A. Kwentus, and A. N. Willson Jr., "A Programmable FIR Digital Filter using CSD Coefficients, " IEEE J. of Solid State Circuits, Vol. 31, No. 6, pp. 869-874, June 1996.
461. [Kwe97] A. Y. Kwentus, Z. Jiang, and Alan N. Wilson, Jr. , "Application of Filter Sharpening to Cascaded Integrator-Comb Decimation Filters, " IEEE Transactions on Signal Processing, Vol. 45, No. 2, pp. 457-467, 1997.
462. [Lee96] H. R. Lee, C. W. Jen, and C. M. Liu, "A New Hardware-Efficient Architecture for Programmable FIR Filters, " IEEE Transactions on Circuits and Systems-II, Vol. 43, No. 9, pp. 637-644, Sept. 1996.
463. [Li93] D. Li, J. Song, and Y. Lim, "Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two Coefficients, " In Proc. IEEE International symposium on Circuits and Systems 1993, Vol. 1, May 1993, pp. 84-87.
464. [Man89] E. D. Man, and T. Noll, "Arrangement for Bit-Parallel Addition of Binary Numbers with Carry-Save Overflow Correction, " U. S. Patent 4, 888, 723, Dec. 19, 1989.
465. [Mor95] F. Moreau de Saint-Martin, and P. Siohan, "Design of Optimal Linear-Phase Transmitter and Receiver Filters for Digital Systems, '' IEEE International Symposium on Circuits and Systems, 1995, Vol. 2, pp. 885-888.
466. [Nol91] T. Noll, "Carry-Save Architectures for High-Speed Digital Signal Processing, " Journal of VLSI Signal Processing, Vol. 3, pp. 121-140, June 1991.
467. [Oh95] W. J. Oh, and Y. H. Lee, "Implementation of Programmable Multiplierless FIR Filters with Powers-of-Two Coefficients, " IEEE Trans. Circuits and Systems II, Vol. 42, No. 8, pp. 553-556, Aug. 1995.
468. [Par89] K. Parhi, and D. Messerschmitt, "Pipeline Interleaving and Parallelism in Recursive Digital Filters-Part I: Pipelining Using Scattered Look-Ahead and Decomposition, " IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 37, No. 7, pp. 1099-1117, July 1989.
469. [Sam88] H. Samueli, "On the Design of Optimal Equiripple FIR Digital Filters for Data Transmission Applications, " IEEE Transactions on Circuits and Systems, Vol. 35, No. 12, pp. 1542-1546, Dec. 1988.
470. [Sam89] H. Samueli, "An Improved Search Algorithm for the Design of Multiplierless FIR Filters with Powers-of-Two Coefficients, " IEEE Transactions on Circuits and Systems, Vol. 36, No. 7, pp. 1044-1047, Jul. 1989.
471. [Sam91] H. Samueli, "On the Design of FIR Digital Data Transmission Filters with Arbitrary Magnitude Specifications, " IEEE Transactions on Circuits and Systems, Vol. 38, No. 12, pp. 1563-1567, Dec. 1991.
472. [Tat90] L. R. Tate, "Truncated Product Partial Canonical Signed Digit Multiplier, " U. S. Patent 4, 967, 388, Oct. 30, 1990.
473. [Vai87] P. Vaidyanathan, and T. Nguyen, "A "Trick'' for the Design of FIR Half-Band Filters, " IEEE Transactions on Circuits and Systems, Vol. 34, No. 3, pp. 297-300, Mar. 1987.
474. [Vai93] P. P. Vaidyanathan, "Multirate Systems and Filter Banks, " Prentice-Hall, 1993.
475. [Whi00] B. A. White, and M. I Elmasry, "Low-Power Design of Decimation Filters for a Digital IF Receiver, " IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 8, No. 3, pp. 339-345, June 2000.
476. [Yag96] M. Yagu, A. Nishihara, and N. Fujii, "Design of FIR Digital Filters Using Estimates of Error Function over CSD Coefficient Space, " IEICE Transactions on Fundamentals, Vol. E79-A, No. 3, pp. 283-290, Mar. 1996.
477. [Zha01] T. Zhangwen, Z. Z. Zhanpeng, Z. Jie, and M. Hao "A High-Speed, Programmable, CSD Coefficient FIR Filter, " in Proc. 13th Annual IEEE International ASIC/SOC Conference, Sept. 2001, pp. 397-400.
478. [Zha88] Q. Zhao, and Y. Tadokoro, "A Simple Design of FIR Filters with Powers-of-Two Coefficients, " IEEE Transactions on Circuits and Systems, Vol. 35, No. 5, pp. 566-570, May 1988.
479. [Ana01] Analog Devices, "Four Channel, 104 MSPS Digital Transmit Signal Processor (TSP), " Preliminary Technical Data AD6623, 2001.
480. [Che93] D. Chester, "A Generalized Rate Change Filter Architecture, " IEEE International Conference on Acoustics, Speech, and Signal Processing 1993, Vol. 3, pp. 181-184.
481. [Che98] D. Chester, "Rate Change Filter and Method, " U. S. Patent 5, 717, 617, Feb. 10, 1998.
482. [Cho01] K. H. Cho, and H. Samueli, "A Frequency-Agile Single-Chip QAM Modulator with Beamforming Diversity, " IEEE Journal of Solid-State Circuits, Vol. 36, No. 3, March 2001, pp. 398-407.
483. [Egi96] K. Egiazarian, T. Saramäki, H. Chugurian, and J. Astola, "Modified B-Spline Interpolators and Filters: Synthesis and Efficient Implementation, " IEEE International Conference on Acoustics, Speech and Signal Processing 1996, Vol. 3, pp. 1743-1746.
484. [Eru93] L. Erup, F. M. Gardner, and R. A. Harris, "Interpolation in Digital Modems-Part II: Implementation and Performance, " IEEE Transactions on Communications, Vol. 41, No. 6, June 1993, pp. 998-1008.
485. [Far98] C. W. Farrow, "A Continuously Variable Digital Delay Element, " in Proc. IEEE International Symposium on Circuits and Systems 1988, pp. 2641-2645.
486. [Fu99] D. Fu, and A. Willson, Jr., "Design of an Improved Interpolation Filter Using a Trigonometric Polynomial, " IEEE International Symposium on Circuits and Systems 1999, Vol. 4, pp. 363-366.
487. [Gar93] F. M. Gardner, "Interpolation in Digital Modems-Part I: Fundamentals, " IEEE Transactions on Communications, Vol. 41, No. 3, March 1993, pp. 501-507.
488. [Got01] A. Gotchev, K. Egiazarian, J. Vesma, and T. Saramäki, "Edge-Preserving Image Resizing Using Modified B-Splines, " IEEE International Conference on Acoustics, Speech, and Signal Processing 2001, Vol. 3, pp. 1865-1868.
489. [Gra01] Graychip, Inc., "Multi-standard Quad DUC Chip, " GC4116 Data Sheet, Rev 1.0, April 2001.
490. [Hen99] M. Henker, T. Hentschel, and G. Fettweis, "Time-Variant CICFilters for Sample Rate Conversion with Arbitrary Rational Factors, " IEEE International Conference on Electronics, Circuits and Systems 1999, Vol. 1, pp. 67-70.
491. [Hou78] H. Hou, and H. Andrews, "Cubic Splines for Image Interpolation and Digital Filtering, " IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. ASSP-26, No. 6, Dec. 1978, pp. 508-517.
492. [Int01] Intersil Corporation, Quad Programmable UpConverter, ISL5217 Data Sheet, File Number 6004, April 2001.
493. [Laa96] T. Laakso, V. Välimäki, M. Karjalainen, and U. Laine, "Splitting the Unit Delay, " IEEE Signal Processing Magazine, Vol. 13, Jan. 1996, pp. 30-60.
494. [Mit98] S. Mitra, "Digital Signal Processing, A Computer-Based Approach, " McGraw-Hill, Singapore 1998.
495. [Ram84] T. A. Ramstad, "Digital Methods for Conversion Between Arbitrary Sampling Frequencies, " IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. ASSP-32, No. 3, June 1984, pp. 577-591.
496. [Sam00] H. Samueli, and J. Laskowski, "Variable Rate Interpolator, " U. S. Patent 6, 144, 712, Nov. 7, 2000.
497. [Sne99] J. Snell, "Interpolator using a Plurality of Polynomial Equations and Associated Methods, " U. S. Patent 5, 949, 695, Sep. 7, 1999.
498. [Uns91] M. Unser, A. Aldroubi, and M. Eden, "Fast B-Spline Transforms for Continuous Image Representation and Interpolation, " IEEE Transactions on Pattern Analysis and Machine Intelligence, Vol. 13, No. 3, March 1991, pp. 277-285.
499. [Väl95] V. Välimäki, "Discrete-Time Modeling of Acoustic Tubes Using Fractional Delay Filters, " Doctoral thesis, Helsinki University of Technology, Espoo, Finland, 1995.
500. [Ves00] J. Vesma, and T. Saramäki, "Design and Properties of Polynomial-Based Fractional Delay Filters, " in Proc. IEEE International Symposium on Circuits and Systems 2000, Vol. 1, pp. 104-107.
501. [Ves95] J. Vesma, "Timing Adjustment in Digital Receivers Using Interpolation, " Master of Science thesis, Tampere University of Technology, Tampere, Finland, 1995.
502. [Ves96a] J. Vesma, and T. Saramäki, "Interpolation Filters with Arbitrary Frequency Response for All-Digital Receivers, " in Proc. IEEE International Symposium on Circuits and Systems 1996, pp. 568-571.
503. [Ves96b] J. Vesma, M. Renfors, and J. Rinne, "Comparison of Efficient Interpolation Techniques for Symbol Timing Recovery, " in Proc. IEEE Globecom 96, London, UK, Nov. 1996, pp. 953-957.
504. [Ves98] J. Vesma, R. Hamila, T. Saramäki, and M. Renfors, "Design of Polynomial Interpolation Filters Based on Taylor Series, " in Proc. IX European Signal Processing Conf., Rhodes, Greece, Sep. 1998, pp. 283-286.
505. [Ves99] J. Vesma, "Optimization and Applications of Polynomial-Based Interpolation Filters, " Doctoral thesis, Tampere University of Technology, Tampere, Finland, 1999.
506. [Bug99] A. R. Bugeja, B. S. Song, P. L. Rakers, and S. F. Gillig, "A 14-b, 100-MS/s CMOS DAC Designed for Spectral Performance, " IEEE J. Solid-State Circuits, Vol. 34, No. 12, pp. 1719-1732, Dec. 1999.
507. [FLE98] FLEX 10K Embedded Programmable Logic Family Data Sheet, Altera Corp., San Jose, CA, Oct. 1998.
508. [GPP00] 3rd Generation Partnership Project; Technical Specification Group d Radio Access Networks; UTRA (BS) FDD; Radio transmission and Reception, 3G TS 25.104, V3.3.0, June 2000.
509. [Kos01] M. Kosunen, J. Vankka, M. Waltari, and K. Halonen, "A Multicarrier QAM Modulator for WCDMA Base Station with on-chip D/A converter, " Proceedings of CICC 2001 Conference, May 6-9 2001, San Diego, USA, pp. 301-304.
510. [Mat94] Matlab Signal Processing Toolbox User's Guide, The Math Works Inc., Natick, Mass., June 1994.
511. [Sam88] Henry Samueli, "The Design of Multiplierless FIR Filters for Compensating D/A Converter Frequency Response Distortion, " IEEE Transactions on Circuits and Systems, Vol. 35, No. 8, pp. 1064-1066, August 1988.
512. [Sam89] Henry Samueli, "An Improved Search Algorithm for the Design of Multiplierless FIR Filters with Powers-of-Two Coefficients, " IEEE Transactions on Circuits and Systems, Vol. 36, No. 7, pp. 1044-1047, July 1989.
513. [Ana02] "AD9744 14-Bit, 165 MSPS TxDAC D/A Converter, " Analog Devices Data Sheet, May 2002.
514. [Azi95] P. M. Aziz, H. V. Sorensen, and J. Van der Spiegel, "Performance of Complex Noise Transfer Functions in Bandpass and Multi Band Sigma Delta Systems, " in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 1995, Vol. 1, pp. 641-644.
515. [Fle98] FLEX 10K Embedded Programmable Logic Family Data Sheet, Altera Corp., San Jose, CA, Oct. 1998.
516. [Ftp] ftp://ftp.mathworks.com/pub/contrib/v5/control/delsig.tar.
517. [Iwa00] M. Iwamoto, A. Jayaraman, G. Hanington, P. F. Chen, A. Bellora, W. Thornton, L. E. Larson, and P. M. Asbeck, "Bandpass Delta-Sigma Class-S Amplifier, " Electronics Letters, Vol. 36, No. 12, pp. 1010-1012, June 2000.
518. [Jan02] I. Janiszewski, B. Hoppe, and H. Meuth, "Numerically Controlled Oscillators with Hybrid Function Generators, " IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Vol. 49, No. 7, pp. 995-1004, July 2002.
519. [Jan97] S. A. Jantzi, K. W. Martin, and A. S. Sedra, "Quadrature Bandpass a Modulation for Digital Radio, " IEEE J. of Solid State Circuits, Vol. 32, No. 12, pp. 1935-1950, Dec. 1997.
520. [Jay98] A. Jayaraman, P. F. Chen, G. Hanington, L. Larson, and P. Asbeck, "Linear High-Efficiency Microwave Power Amplifiers Using Bandpass Delta-Sigma Modulators, " IEEE Microwave and Guided Wave Letters, Vol. 8, No. 3, pp. 121-123, March 1998.
521. [Jen95] J. F. Jensen, G. Raghavan, A. E. Cosand, and R. H. Walden, "A 3.2-GHz Second-Order Delta-Sigma Modulator Implemented in InP HBT Technology, " IEEE J. of Solid State Circuits, Vol. 30, No. 10, pp. 1119-1127, Oct. 1995.
522. [Key01] J. Keyzer, J. Hinrichs, A. Metzger, M. Iwamoto, I. Galton, and P. Asbeck, "Digital Generation of RF Signals for Wireless Communications with Band-Pass Delta-Sigma Modulation, " IEEE Microwave Symposium Digest, Vol. 3, pp. 2127-2130, 2001.
523. [Kos01] M. Kosunen, J. Vankka, M. Waltari, and K. Halonen, "A Multicarrier QAM Modulator for WCDMA Base Station with on-chip D/A converter, " In Proc. 2001 IEEE Custom Integrated Circuits Conference, May 2001, pp. 301-304.
524. [Mag97] A. J. Magrath, and M. B. Sandler, "Digital Power Amplification Using Sigma-Delta Modulation and Bit Flipping, " J. Audio Eng. Soc., Vol. 45, No. 6, pp. 476-487, June 1997.
525. [McC84] R. D. McCallister, and D. Shearer, III, "Numerically Controlled Oscillator Using Quadrant Replication and Function Decomposition, " U. S. Patent 4, 486, 846, Dec. 4, 1984.
526. [Nic91] H. T. Nicholas, and H. Samueli, "A 150-MHz Direct Digital Frequency Synthesiser in 1.25-μm CMOS with-90-dBc Spurious Performance, " IEEE J. Solid-State Circuits, Vol. 26, pp. 1959-1969, Dec. 1991.
527. [Nor97] S. R. Norsworthy, R. Schreier, and G. C. Temes, "Delta-sigma Data Converters, Theory, Design, and Simulation, " New York: IEEE Press, 1997.
528. [Sch03] W. Schofield, D. Mercer, and L. St. Onge, "A 16b 400MS/s DAC with <-80dBc IMD to 300 MHz and <-160dBm/Hz Noise Power Spectral Density," ISSCC Digest of Technical Papers, February 2003, San Francisco, USA, pp. 126-127.
529. J. Vankka, and K. Halonen, "Direct Digital Synthesizers: Theory, Design and Applications, "Kluwer Academic Publishers, 2001.
530. [Van98] J. Vankka, M. Waltari, M. Kosunen, and K. Halonen, "Direct Digital Syntesizer with on-Chip D/A-converter, " IEEE Journal of Solid-State Circuits, Vol. 33, No. 2, pp. 218-227, Feb. 1998.
531. [Bas98] J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 12-bit Intrinsic Accuracy High-Speed CMOS DAC, " IEEE J. Solid-State Circuits, Vol. 33, No. 12, pp. 1959-1969, Dec. 1998.
532. [Bos01] A. Van den Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, "A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter, " IEEE J. Solid-State Circuits, Vol. 36, No. 3, pp. 315-324, Mar. 2001.
533. [Che95] H. H. Chen, and S. E. Schuster, "On-Chip Decoupling Capacitor Optimization for High-Performance VLSI Design, " in Proc. International Symposium on VLSI Technology, Systems, and Applications, 1995, pp. 99-103.
534. [Chi94] S. Y. Chin, and C. Y. Wu, "A 10-bit 125-MHz CMOS Digital-to-Analog Converter (DAC) with Threshold-Voltage Compensated Current Sources, " IEEE J. of Solid State Circuits, Vol. 29, No. 11, pp. 1374-1380, Nov. 1994.
535. [Dar70] S. Darlington, "On Digital Single-Sideband Modulators, " IEEE Trans. Circuit Theory, Vol. 17, No. 3, pp. 409-414, Aug. 1970.
536. [FDD00] 3rd Generation Partnership Project; Technical Specification Group Radio Access Networks; UTRA (BS) FDD; Radio transmission and Reception, 3G TS 25.104, V3.3.0, June 2000.
537. [GSM99] GSM Recommendation 05.05: "Radio Transmission and Reception," Dec. 1999.
538. [Kos01] M. Kosunen, J. Vankka, M. Waltari, and K. Halonen, "A Multicarrier QAM Modulator for WCDMA Basestation with on-chip D/A Converter, " Proceedings of CICC 2001 Conference, May 6-9 2001, San Diego, USA, pp. 301-304.
539. [Lar95] P. Larsson, "Analog Phenomena in Digital Circuits, " Ph.D. dissertation, No. 376, Linköping University, Linköping, Sweden, 1995.
540. [Lar97] P. Larsson, "di/dt Noise in CMOS Integrated Circuits, " Analog Integrated Circuits and Signal Processing, Vol. 14, pp. 113-129, Sept. 1997.
541. [Lar98] P. Larsson, "Resonance and Damping in CMOS Circuits with On-Chip Decoupling Capacitance, " IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 45, No. 8, Aug. 1998, pp. 849-858.
542. [Tak91] H. Takakura, M. Yokoyama, and A. Yamaguchi, "A 10 bit 80MHz Glitchless CMOS D/A Converter, " in Proc. IEEE Custom Integrated Circuits Conf., 1991, pp. 26.5.1-26.5.4.
543. [Van01] J. Vankka, and K. Halonen, "Direct Digital Synthesizers: Theory, Design and Applications," Kluwer Academic Publishers, 2001.
544. [Van02] J. Vankka, J. Ketola, O. Väänänen, J. Sommarek, M. Kosunen, and Kari Halonen, "A GSM/EDGE/WCDMA Modulator with on-chip D/A Converter for Base Station, " ISSCC Digest of Technical Papers, February 3-7, 2002, San Francisco, USA, pp. 236-237.
545. [Won91] B. C. Wong, and H. Samueli, "A 200-MHz All-Digital QAM Modulator and Demodulator in 1.2-μm CMOS for Digital Radio Applications, " IEEE J. Solid-State Circuits, Vol. 26, No. 12, pp. 1970-1979, Dec. 1991.
546. [Wu95] T. Y. Wu, C. T. Jih, J. C. Chen, and C. Y. Wu, "A Low Glitch 10-bit 75-MHz CMOS Video D/A Converter, " IEEE J. Solid-State Circuits, Vol. 30, No. 1, pp. 68-72, Jan. 1995.
547. [Ana01] "AD6623 Four Channel, 104 MSPS Digital Transmit Signal Processor (TSP), " Analog Devices Preliminary Technical Data Sheet, May 2001.
548. [Bel74] M. G. Bellanger, and J. L. Daguet, "TDM-FDM Transmultiplexer: Digital Polyphase and FFT, " IEEE Trans. on Commun., Vol. COM-22, pp. 1199-1204, Sept. 1974.
549. [Bha99] Bhatnagar, H, Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler™ and PrimeTime®, Kluwer Academic Publishers, USA 1999.
550. [Bos01] A. Van den Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, "A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter, " IEEE J. Solid-State Circuits, Vol. 36, No. 3, pp. 315-324, Mar. 2001.
551. [Cho01] K. H. Cho, and H. Samueli, "A Frequency-Agile Single-Chip QAM Modulator with Beamforming Diversity, " IEEE J. of Solid State Circuits, Vol. 36, No. 3, pp. 398-407, Mar. 2001.
552. [Cor90] I. R. Corden, and R. A. Carrasco, "Fast Transform Based Complex Transmultiplexer Algorithm for Multiband Quadrature Digital Modulation Schemes, " IEE Proceedings, Vol. 137, Pt. 1, No. 6, pp. 408-416, Dec. 1990.
553. [Dig99] Digital cellular telecommunication system (Phase 2+); Modulation (GSM 05.04) V8.1.0, European Telecommunications Standards Institute, December 1999.
554. [Eru93] L. Erup, F. M. Gardner, and R. A. Harris, "Interpolation in Digital Modems-Part II: Implementation and Performance, " IEEE Trans. on Commun., Vol. COM-41, pp. 998-1008, June 1993.
555. [Far88] C. W. Farrow, "A Continuously Variable Digital Delay Element, " in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), June 1988, pp. 2641-2645.
556. [FDD00] 3rd Generation Partnership Project; Technical Specification Group Radio Access Networks; UTRA (BS) FDD; Radio transmission and Reception, 3G TS 25.104, V3.3.0, June 2000.
557. [Fli92] N. J. Fliege, and J. Wintermantel, "Complex Digital Oscillators and FSK Modulators, " IEEE Trans. on Signal Processing, Vol. SP-40, No. 2, pp. 333-342, Feb. 1992.
558. [Fli94] N. J. Fliege, Multirate Digital Signal Processing, John Wiley & Sons, 1994.
559. [Fur99] A. Furuskär, S. Mazur, F. Muller, and H. Olofsson, "EDGE: Enhanced Data Rates for GSM and TDMA/136 Evolution, " IEEE Personal Communications, June 1999, pp. 56-66.
560. [GPP00a] 3GPP Technical Specification Group Radio Access Network, Spreading and Modulation (FDD), TS 25.213 V3.2.0, March 2000.
561. [GPP00b] 3GPP Technical Specification Group Radio Access Network, UTRA (BS) FDD; Radio transmission and Reception, TS 25.104 V3.3.0, June 2000.
562. [GPP00c] 3GPP Technical Specification Group GERAN, Digital cellular telecommunication system (Phase 2+); Radio transmission and reception, TS 05.05 V8.6.0, September 2000.
563. [Gra01] "GC4116 Multi-standard Quad DUC Chip, " Graychip Data Sheet, April 2001.
564. [GSM99a] GSM Recommendation 05.04: "Modulation," Dec. 1999.
565. [GSM99b] GSM Recommendation 05.02: "Digital Cellular Telecommunications System (Phase 2+); Multiplexing and Multiple Access on the Radio Path," July 1999.
566. [GSM99c] GSM Recommendation 05.05: "Radio Transmission and Reception," Dec. 1999.
567. [Hau93] J. C. Hausman, R. R. Harnden, E. G. Cohen, and H. G. Mills, "Programmable Canonic Signed Digit Filter Chip, " U. S. Patent 5, 262, 974, Nov. 16, 1993.
568. [Im00] S. Im, W. Lee, C. Kim, Y. Shin, S. H. Lee, and J. Chung, "Implementation of SDR-Based Digital IF Channelizer/De-Channelizer for Multiple CDMA Signals, " IEICE Trans. Commun., Vol. E83-B, No. 6, pp. 1282-1289, June 2000.
569. [Int01] "ISL5217 Quad Programmable UpConverter, " Intersil Corporation Data Sheet, April 2001.
570. [Jun94] P. Jung, "Laurent's Representation of Binary Digital Continuous Phase Modulated Signals with Modulation Index 1/2 Revisited, " IEEE Transactions on Communications, Vol. 42, No. 2/3/4, February/March/April 1994, pp. 221-224.
571. [Ket03] J. Ketola, J. Vankka, and K. Halonen, "Synchronization of Fractional Interval Counter in Non-Integer Ratio Sample Rate Converters, " in Proc. ISCAS'03, Vol. II, May 2003, pp. 89-92.
572. [Kos01] M. Kosunen, J. Vankka, M. Waltari, and K. Halonen, "A Multicarrier QAM Modulator for WCDMA Basestation with on-chip D/A Converter, " in Proc. Custom Integrated Circuits Conf., May 2001, San Diego, USA, pp. 301-304.
573. [Kur82] C. F. Kurth, K. J. Bures, P. R. Gagnon, and M. H. Etzel, "A Per-Channel, Memory-Oriented Transmultiplexer with Logarithmic Processing, " IEEE Trans. on Commun., Vol. COM-30, pp. 1520-1527, July 1982.
574. [Lau86] P. Laurent, "Exact and Approximate Construction of Digital Phase Modulations by Superposition of Amplitude Modulated Pulses (AMP), " IEEE Transactions on Communications, Vol. COM-34, No. 2, February 1986, pp. 150-160.
575. [Mur81] K. Murota, "GMSK Modulation for Digital Mobile Radio Telephony, " IEEE Transactions on Communications, Vol. 29, pp. 1044-1050, July 1981.
576. [Par99] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley & Sons, 1999.
577. [Paš01] R. Paško, L. Rijnders, P. R. Schaumont, S. A. Vernalde, and D. Duraková, "High-Performance Flexible all-digital Quadrature up and down Converter Chip, " IEEE J. of Solid State Circuits, Vol. 36, No. 3, pp. 408-416, Mar. 2001.
578. [Sam88] H. Samueli, "The Design of Multiplierless FIR Filters for Compensating D/A Converter Frequency Response Distortion, " IEEE Trans. Circuits and Syst., Vol. 35, No. 8, pp. 1064-1066, Aug. 1988.
579. [Sam89] H. Samueli, "An Improved Search Algorithm for the Design of Multiplierless FIR Filters with Powers-of-Two Coefficients, " IEEE Trans. Circuits and Syst., Vol. 36, No. 7, pp. 1044-1047, July 1989.
580. [Sam91] H. Samueli, "On the Design of FIR Digital Data Transmission Filters with Arbitrary Magnitude Specifications, " IEEE Transactions on Circuits and Systems, Vol. 38, No. 12, Dec. 1991, pp. 1563-1567.
581. [Sch81] H. Scheuermann, and H. Göckler, "A Comprehensive Survey of Digital Transmultiplexing Methods, " Proc. of IEEE, Vol. 69, No. 11, pp. 1419-1450, Nov. 1981.
582. [Stu81] W. L. Stutzman, and G. A. Thiele, "Antenna Theory and Design, " John Wiley & Sons, Inc. 1981.
583. [Syn99] Synopsys, Behavioral Compiler Reference Manual, v1999.05.
584. [Tak91] H. Takakura, M. Yokoyama, and A. Yamaguchi, "A 10 bit 80MHz Glitchless CMOS D/A Converter, " in Proc. IEEE Custom Integrated Circuits Conf., 1991, pp. 26.5.1-26.5.4.
585. [TDD00] 3rd Generation Partnership Project; Technical Specification Group Radio Access Networks; UTRA (BS) TDD; Radio transmission and Reception, 3G TS 25.105, V3.3.0, June 2000.
586. [Tsu78] T. Tsuda, S. Morita, and Y. Fujii, "Digital TDM-FDM Translator with Multistage Structure, " IEEE Trans. on Commun., Vol. COM-26, pp. 734-741, May 1978.
587. [Van00] J. Vankka, M. Kosunen, I. Sanchis, and K. Halonen, "A Multicarrier QAM Modulator, " IEEE Trans. on Circuits and Systems Part II, Vol. 47, No. 1, pp. 1-10, Jan. 2000.
588. [Van01a] J. Vankka, and K. Halonen, "Direct Digital Synthesizers: Theory, Design and Applications," Kluwer Academic Publishers, 2001.
589. [Van01b] J. Vankka, M. Honkanen, and K. Halonen, "A Multicarrier GMSK Modulator, " IEEE Journal on Selected Areas in Communications, Vol. 19, No. 6, pp. 1070-1079, June 2001.
590. [Van02] J. Vankka, J. Ketola, J. Sommarek, Olli Väänänen, M. Kosunen, and K. Halonen, "A GSM/EDGE/WCDMA Modulator with on-chip D/A Converter for Base Stations, " IEEE Trans. on Circuits and Systems Part II, Vol. 49, No. 10, pp. 645-655, Oct. 2002.
591. [Vol59] J. E. Volder, "The CORDIC Trigonometric Computing Technique, " IRE Trans. on Electron. Comput., Vol. C-8, pp. 330-334, Sept. 1959.
592. [GPP00] 3GPP Technical Specification Group Access Network Base station conformance testing, TS 25.141 V3.2.0. 2000.
593. [Gro94] R. Gross, and D. Veeneman, "SNR and Spectral Properties for a Clipped DMT ADSL Signal, " IEEE International Conference on Communications, 1994, Vol. 2, pp. 843-847.
594. [Mil98] S. L. Miller, and R. J. O'Dea, "Peak Power and Bandwidth Efficient Linear Modulation, " IEEE Transactions on Communications, Vol. 46, No. 12, pp. 1639-1648, Dec. 1998.
595. [Nee98] R. van Nee, and A. de Wild, "Reducing the Peak-to-Average Power Ratio of OFDM, " IEEE Vehicular Technology Conference, 1998, Vol. 3, pp. 2072-2076.
596. [Ozl95] F. M. Ozluturk, and G. Lomp, "Effect of Limiting the Downlink Power in CDMA Systems with or without Forward Power Control, " IEEE Military Communications Conference, 1995, pp. 952-956.
597. [Pau96] M. Pauli, and H.-P, Kuchenbecker, "Minimization of the Intermodulation Distortion of a Nonlinearly Amplified OFDM Signal, " Wireless Personal Communications 4: pp. 90-101, 1996.
598. [Vää01] O. Väänänen, "Clipping in Wideband CDMA Base Station Transmitter, " Master's Thesis, Helsinki University of Technology, 2001.
599. [Yan00] Y. Hong-Kui, "Method & Apparatus for Reducing the Peak Power Probability of a Spread Spectrum Signal, " European Patent Application EP1058400, Dec. 6, 2000.
600. R. N. Braithwaite, "Using Walsh Code Selection to Reduce the Power Variance of Band-Limited Forward-Link CDMA Waveforms, " IEEE Journal on Selected Areas in Communications, Vol. 18, No. 11, pp. 2260-2269, Nov. 2000.
601. V. K. N. Lau, "Peak-to-average ratio (PAR) Reduction by Walsh-Code Selection for IS-95 and CDMA2000 Systems, " IEE Proceedings-Communications, Vol. 147, No. 6, pp. 361-364, Dec. 2000.
602. J. Armstrong, "New OFDM Peak-to-Average Power Reduction Scheme, " IEEE Vehicular Technology Conference, 2001, Vol. 1, May 2001, pp. 756-760.
603. J. Tellado, and J. M. Cioffi, "Efficient Algorithms for Reducing PAR in Multicarrier Systems, " IEEE International Symposium on Information Theory, Aug. 1998, pp. 191.
604. T. Wada, T. Yamazato, M. Katayama, and A. Ogawa, "A Constant Amplitude Coding for Orthogonal Multi-code CDMA Systems, " IEICE Trans. fundamentals, Vol. E80-A. No. 12, pp. 2477-2484, Dec. 1997.