A 10-b, 100-MS/s CMOS A/D converter

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 3, 1997, Pages 302-311

  Kim, Kwang Young ^a,b,c,d,e,f   Kusayanagi, Naoya ^b,e,g,h,i,j   Abidi, Asad A ^{a,b,k,l,m,n,o}  

^a IEEE

^b University of California   (United States)

^c Seoul National University   (South Korea)

^d MARQUETTE UNIVERSITY   (United States)

^e UNIVERSITY OF CALIFORNIA   (United States)

^f Rockwell Semiconductor Systems   (United States)

^g SOPHIA UNIVERSITY   (Japan)

^h Hokushin Electric Works ^*

ⁱ YOKOGAWA ELECTRIC CORPORATION   (Japan)

^j Institute of Electronics   (Japan)

^k IMPERIAL COLLEGE LONDON   (United Kingdom)

^l UNIVERSITY OF CALIFORNIA   (United States)

^m LUCENT TECHNOLOGIES   (United States)

ⁿ Technical Staff

^o HEWLETT PACKARD LABORATORIES   (United States)

more..

Author keywords

Analog integrated circuit; Analog digital conversion; CMOS analog integrated circuits; Digital analog conversion; Mixed analog digital integrated circuits; Operational amplifier; Sample and hold circuits; Switched capacitor circuits

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; LINEAR INTEGRATED CIRCUITS; OPERATIONAL AMPLIFIERS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; SIGNAL TO NOISE RATIO;

ANALOG INTEGRATED CIRCUITS; SWITCHED CAPACITOR CIRCUITS;

ANALOG TO DIGITAL CONVERSION;

EID: 0031102975     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.557627     Document Type: Article

References (24)

1. R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, "A 10 b 75 MSPS subranging A/D converter with integrated sample and hold," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1339-1346, 1990.
2. P. Vorenkamp and J. P. M. Verdaasdonk, "A 10 b 50 MS/s pipelined ADC," in Int. Solid-State Circuits Conf., San Francisco, CA, 1992, pp. 32-33.
3. W. T. Colleran and A. A. Abidi, "A 10-b, 75-MHz two-stage pipelined bipolar A/D converter," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1187-1199, 1993.
4. K. Sone, Y. Nishida, and N. Nakadai, "A 10-b 100-Msample/s pipelined subranging BiCMOS ADC," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1180-1186, 1993.
5. F. Murden and R. Gosser, "12 b 40 M Sample/s two-stage A/D converter," in Int. Solid-State Circuits Conf., San Francisco, CA, 1995, pp. 216-217.
6. B. Nauta and A. G. W. Venes, "A 70 MSample/s 110 mW 8 b CMOS folding interpolating A/D converter," in Int. Solid-State Circuits Conf., San Francisco, CA, 1995, pp. 214-215.
7. W. C. Black, Jr. and D. A. Hodges, "Time interleaved converter arrays," IEEE. J. Solid-State Circuits. vol. SC-15, no. 6, pp. 1022-1029, 1980.
8. Y.-C. Jenq, "Digital spectra of nonuniformly sampled signals: Fundamental and high-speed waveform digitizers," IEEE Trans. Instrum. Meas., vol. 37, no. 6, pp. 245-251, 1988.
9. K. Poulton, J. J. Corcoran, and T. Hornak, "A I GHz 6 bit ADC system," IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 962-970, 1987.
10. S. H. Lewis and P. R. Gray, "A pipelined 5 MS/s 9-bit analog to digital converter," IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 954-961, 1987.
11. C. S. G. Conroy, D. W. Cline, and P. R. Gray, "An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 447-154, 1993
12. M. Yotsuyanagi, T. Etoh, and K. Hirata, "A 10-b 50-MHz pipelined CMOS A/D converter with S/H," IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 292-300, 1993
13. K. Nakamura, M. Hotta, L. R. Carley, and D. J. Allstot, "An 85 mW. 10 b, 40 Msample/s CMOS parallel-pipelined ADC," IEEE J. Solid-State Circuits. vol. 30, no. 3, pp. 173-183, 1995.
14. Y.-M. Lin, B. Kim, and P. R. Gray, "A 13 b, 2.5 MHz self-calibrated pipelined A/D converter in 3-micron CMOS," IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 628-636, 1991.
15. G. Nicollini, P. Confalonieri, and D. Senderowicz, "A fully differential sample-and-hold circuit for high-speed applications," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1461-1465, 1989.
16. K. Bult and G. Geelen, "A fast settling CMOS Op Amp for SC-circuits with 90 dB DC-gain," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1379-1384, 1990.
17. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440, 1989.
18. T. Miki, H. Kouno, T. Kumamoto, Y. Kinoshita, T. Igarashi, and K. Okada, "A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter," IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 516-522, 1994.
19. C. W. Mangelsdorf, "A 400-MHz input flash converter with error correction," IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 184-191, 1990.
20. M. J. M. Pelgrom, "A 10 b 50 MHz CMOS D/A converter with 75-Ohm buffer," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1347-1352, 1990.
21. K. Y. Kim and A. A. Abidi, "A CMOS signal conditioning interface IC for CCD imagers," in Int. Symp. VLSI Technology, Systems, and Applications, Taipei, 1993, pp. 277-281.
22. A. G. W. Venes and R. van de Plassche, "An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing," in Int. Solid-State Circuits, Conf., San Francisco, 1996, pp 318-319.
23. R. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters. Dordrecht. The Netherlands: Kluwer, 1994.
24. T. B. Cho, D. W. Cline, C. S. G. Conroy, and P. R. Gray. "Design considerations for low-power, high-speed CMOS analog/digital converters," in Symp. Low Power Electronics, San Diego. CA, 1994, pp. 70-73.