A 10-bit charge-redistribution ADC consuming 1.9 μw at 1 MS/s

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 5, 2010, Pages 1007-1015

  Van Elzakker, Michiel ^a,b   Van Tuijl, Ed ^a,c   Geraedts, Paul ^a   Schinkel, Daniël ^a,c   Klumperink, Eric A M ^a   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b ItoM   (Netherlands)

^c Axiom IC Twente   (Netherlands)

Author keywords

ADC; Analog to digital converter; Asynchronous; Charge redistribution; CMOS; Comparators; DAC; Digital to analog converter; Dynamic power dissipation; Figure of merit; Low noise; Low power; Low static current; Sense amplifiers; Sensors; Smart dust

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; CMOS COMPARATORS; DAC; DIGITAL-TO-ANALOG CONVERTERS; FIGURE OF MERIT; LOW NOISE; LOW POWER; SMART DUST; STATIC CURRENTS;

APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; COMPARATORS (OPTICAL); DUST; ENERGY EFFICIENCY; FREQUENCY CONVERTERS; HYBRID COMPUTERS; SENSORS;

DIGITAL INTEGRATED CIRCUITS;

EID: 77951681747     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2043893     Document Type: Article

References (25)

1. B. W. Cook, S. Lanzisera, and K. S. J. Pister, "SoC issues for RF smart dust", Proc. IEEE, vol. 94, no. 6, pp. 1177-1196, Jun. 2006.
2. B. Murmann, "A/D converter trends: Power dissipation, scaling and digitally assisted architectures", in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 21-24, 2008, pp. 105-112.
3. R. van de Plassche, Integrated Analog-to-Digital and Dig-ital-to-Analog Converters. Boston, MA: Kluwer Academic, 1994, ISBN 0-7923-9436-4.
4. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, "A 1.9 μ W 4.4 fJ/conversion-step 10 b 1 MS/s charge-redistribution ADC", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008.
5. J. McCreary and P. Gray, "All-MOS charge redistribution analog-to-digital conversion techniques", IEEE J. Solid-State Circuits, vol. 10, no. 6, pp. 371-379, Dec. 1975.
6. B. Ginsburg and A. Chandrakasan, "An energy-efficient charge recycling approach for a SAR converter with capacitive DAC", in Proc. IEEEISCAS, May. 2005. vol. 1, pp. 184-187.
7. 2", in IEEE Symp. Low Power Electronics, 1994.
8. C. Saas, A. Wroblewski, and J. A. Nossek, "Low-power DA-converters for display applications using stepwise charging and charge recovery", in Proc. ISCAS 2004.
9. A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog to-digital converter", IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May. 1999.
10. D. Schinkel, E. Mensink, and E. Klumperink et al., "A double-tail latch-type voltage sense amplifier with 18 ps Setup+Hold time", in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 314-315.
11. E. Zimmermann, A. Verweerd, W. Glaas, A. Tillmann, and A. Kemna, "An AMR sensor-based measurement system for magnetoelectrical resistivity tomography", IEEE Sensors J., vol. 5, no. 2, pp. 233-241, Apr. 2005.
12. T. Sepke, P. Holloway, C. G. Sodini, and H. S. Lee, "Noise analysis for comparator-based circuits", IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 56, no. 3, pp. 541-553, Mar. 2009.
13. B. Murmann, "ADC Performance Survey 1997-2009", [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html
14. J. Craninckx and G. van der Plas, "A 65 fJ/conversion-step 0-to-50 MS/s 0-to-0.7 mW 9 b charge-sharing SAR ADC in 90 nm digital CMOS", in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 246-247.
15. G. Van der Plas and B. Verbruggen, "A 150 MS/s 133 uW 7 b ADC in 90 nm digital CMOS using a comparator-based asynchronous binary-search sub-ADC", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008.
16. B. Verbruggen, J. Cranickx, M. Kuijk, P. Wambacq, and G. Van der Plas, "A 2.2 mW 5 b 1.75 GS/s folding flash ADC in 90 nm digital CMOS", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008.
17. V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. vd Plas, and J. Craninckx, "An 820 μ W 9 b 40 MS/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008.
18. A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, "A 9.4-ENOB 1 V 3.8 μ W 100 kS/s SAR ADC with time-domain comparator", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008.
19. M. Boulemnakher, E. Andre, J. Roux, and F. Paillardet, "A 1.2 V 4.5 mW 10 b 100 MS/s pipelined ADC in 65 nm CMOS", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008.
20. L. Brooks and H. Lee, "A 12 b 50 MS/s fully differential zero-crossing-based ADC without CMFB", in IEEE ISSCC Dig. Tech. Papers, Feb. 2009.
21. G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, E. Ro-mani, A. Melodia, and V. Melini, "A 14 b 20 mW 640 MHz CMOS CT delta sigma ADC with 20 MHz signal bandwidth and 12 b ENOB", in IEEE ISSCC Dig. Tech. Papers, Feb. 2006.
22. D. Daly and A. Chandrakasan, "A 6 b 0.2-to-0.9 V highly-digital flash ADC with comparator redundancy", in IEEE ISSCC Dig. Tech. Papers, Feb. 2008.
23. Y. Lin, S. Chang, Y. Liu, C. Liu, and G. Huang, "A 5 b 800 MS/s 2 mW asynchronous binary-search ADC in 65 nm CMOS", in IEEE ISSCC Dig. Tech. Papers, Feb. 2009.
24. R. van Veldhoven, "A tri-mode continuous time ΔΣ modulator with switched cap feedback for GSM-EDGE/CDMA2000/UMTS receiver", in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 64-65.
25. J. Hu, N. Dolev, and B. Murmann, "A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification", in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2008, pp. 216-217.