Feed-forward approach for timing skew in interleaved and double-sampled circuits

Electronics Letters

Volumn 37, Issue 9, 2001, Pages 552-554

  Manganaro, G ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CAPACITORS; LOGIC GATES; PHASE MODULATION; SPECTRUM ANALYSIS; SWITCHING;

CLOCK GENERATORS;

TIMING CIRCUITS;

EID: 0035953717     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20010384     Document Type: Article

References (8)

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2. FU, D., DYER, K.C., LEWIS, S.H., and HURST, P.J.: 'A digital background calibration technique for time-interleaved analog-to-digital converters', IEEE J. Solid-State Circuits, 1998, 33, (12), pp. 1904-1911
3. DYER, K.C., FU, D., LEWIS, S.H., and HURST, P.J.: 'An analog background calibration technique for time-interleaved analog-to-digital converters', IEEE J. Solid-State Circuits, 1998, 33, (12), pp. 1912-1919
4. GUSTAVSSON, M., and TAN, N.N.: 'A global passive sampling technique for high-speed switched-capacitor time-interleaved ADCs', IEEE Trans. Circuits Syst. II, 2000, 47, (9), pp. 821-831
5. JENQ, Y.-C.: 'Digital spectra of nonuniformly sampled signals: fundamentals and high-speed waveform digitizers', IEEE Trans. Instrum. Meas., 1988, 37, pp. 245-251
6. WALTARI, M., and HALONEN, K.: 'Timing skew insensitive switching for double-sampled circuits'. Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), May 1999, Vol. 2, pp. 61-64
7. SUMANEN, L., WALTARI, M., and HALONEN, K.: 'A 10-bit 200MS/S CMOS parallel pipeline A/D converter'. Proc. 26th European Solid-State Circuits Conf. (ESSCIRC), Sept. 2000, pp. 440-443
8. PARK, Y.-I., SOUNDARAPANDIAN, K., TSAY, F., and BARTOLOME, E.: 'A 1.8V, 10-bit, 100MS/s CMOS pipelined ADC'. 2001 IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 2001