-
2
-
-
49549112502
-
A 100 mW 10 MHz-BW CT AS modulator with 87 dB DR and 91 dBc IMD
-
Feb
-
W. Yang, W. Schofield, H. Shibata, S. Korrapati, A. Shaikh, N. Abaskharoun, and D. Ribner, "A 100 mW 10 MHz-BW CT AS modulator with 87 dB DR and 91 dBc IMD", in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008, pp. 498-499.
-
(2008)
IEEE Int. Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers
, pp. 498-499
-
-
Yang, W.1
Schofield, W.2
Shibata, H.3
Korrapati, S.4
Shaikh, A.5
Abaskharoun, N.6
Ribner, D.7
-
3
-
-
33845630644
-
A 20-mW 640-MHz CMOS continuous-time AS ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB
-
Dec
-
G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holugigue, and E. Romani, "A 20-mW 640-MHz CMOS continuous-time AS ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB", IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2641-2649, Dec. 2006.
-
(2006)
IEEE J. Solid-state Circuits
, vol.41
, Issue.12
, pp. 2641-2649
-
-
Mitteregger, G.1
Ebner, C.2
Mechnig, S.3
Blon, T.4
Holugigue, C.5
Romani, E.6
-
4
-
-
70349283738
-
A 0.13μm CMOS 78 dB SNDR 87 mW 20 MHz BW CT AS ADC with VCO-based integrator and quantizer
-
Feb
-
M. Park and M. Perrott, "A 0.13μm CMOS 78 dB SNDR 87 mW 20 MHz BW CT AS ADC with VCO-based integrator and quantizer", in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, pp. 170-171.
-
(2009)
IEEE Int. Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers
, pp. 170-171
-
-
Park, M.1
Perrott, M.2
-
5
-
-
70349271262
-
A 20 mHz BW 68 dB DR CT AS ADC based on a multi-bit time-domain quantizer and feedback element
-
Feb
-
V. Dhanasekaran, M. Gambhir, M. M. Elsayed, E. Sánchez-Sinencio, J. Silva-Martinez, C. Mishra, L. Chen, and E. Pankratz, "A 20 mHz BW 68 dB DR CT AS ADC based on a multi-bit time-domain quantizer and feedback element", in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, pp. 174-175.
-
(2009)
IEEE Int. Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers
, pp. 174-175
-
-
Dhanasekaran, V.1
Gambhir, M.2
Elsayed, M.M.3
Sánchez-Sinencio, E.4
Silva-Martinez, J.5
Mishra, C.6
Chen, L.7
Pankratz, E.8
-
6
-
-
0030784975
-
Delta-sigma modulators using frequency-modulated intermediate values
-
Jan
-
M. Høvin, A. Olsen, T. S. Lande, and C. Toumazou, "Delta-sigma modulators using frequency-modulated intermediate values", IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 13-22, Jan. 1997.
-
(1997)
IEEE J. Solid-state Circuits
, vol.32
, Issue.1
, pp. 13-22
-
-
Høvin, M.1
Olsen, A.2
Lande, T.S.3
Toumazou, C.4
-
7
-
-
34547339903
-
A time-based analog-to-digital converter using a multi-phase voltage-controlled oscillator
-
May
-
J. Kim and S. Cho, "A time-based analog-to-digital converter using a multi-phase voltage-controlled oscillator", in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), May 2006, pp. 3934-3937.
-
(2006)
Proc. IEEE Int. Symp. Circuits and Systems (ISCAS)
, pp. 3934-3937
-
-
Kim, J.1
Cho, S.2
-
8
-
-
0034230321
-
Time-referenced single-path multi-bit AS ADC using a VCO-based quantizer
-
Jul
-
R. Naiknaware, H. Tang, and T. Fiez, "Time-referenced single-path multi-bit AS ADC using a VCO-based quantizer", IEEE Trans. Circuits Syst. II: Analog Digital Signal Process., vol. 47, no. 7, pp. 596-602, Jul. 2000.
-
(2000)
IEEE Trans. Circuits Syst. II: Analog Digital Signal Process.
, vol.47
, Issue.7
, pp. 596-602
-
-
Naiknaware, R.1
Tang, H.2
Fiez, T.3
-
9
-
-
0032688006
-
The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer
-
Jul
-
A. Iwata, N. Sakimura, M. Nagata, and T. Morie, "The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer", IEEE Trans. Circuits Syst. II: Analog Digital Signal Process., vol. 46, no. 7, pp. 941-945, Jul. 1999.
-
(1999)
IEEE Trans. Circuits Syst. II: Analog Digital Signal Process.
, vol.46
, Issue.7
, pp. 941-945
-
-
Iwata, A.1
Sakimura, N.2
Nagata, M.3
Morie, T.4
-
10
-
-
44849092543
-
A 0.2 V, 7.5 μW, 20 kHz S A modulator with 69 dB SNR in 90 nm CMOS
-
Sep
-
U. Wismar, D. Wisland, and P. Andreani, "A 0.2 V, 7.5 μW, 20 kHz S A modulator with 69 dB SNR in 90 nm CMOS", in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2007, pp. 206-209.
-
(2007)
Proc. European Solid-state Circuits Conf. (ESSCIRC)
, pp. 206-209
-
-
Wismar, U.1
Wisland, D.2
Andreani, P.3
-
12
-
-
41549118015
-
A 12-bit, 10-MHz bandwidth, continuous-time S A ADC with a 5-bit, 950-MS/s VCO-based quantizer
-
Apr
-
M. Z. Straayer and M. H. Perrott, "A 12-bit, 10-MHz bandwidth, continuous-time S A ADC with a 5-bit, 950-MS/s VCO-based quantizer", IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805-814, Apr. 2008.
-
(2008)
IEEE J. Solid-state Circuits
, vol.43
, Issue.4
, pp. 805-814
-
-
Straayer, M.Z.1
Perrott, M.H.2
-
14
-
-
33749391240
-
Digital background correction of harmonic distortion in pipelined ADCs
-
Sep
-
A. Panigada and I. Galton, "Digital background correction of harmonic distortion in pipelined ADCs", IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 53, no. 9, pp. 1885-1895, Sep. 2006.
-
(2006)
IEEE Trans. Circuits Syst. I: Reg. Papers
, vol.53
, Issue.9
, pp. 1885-1895
-
-
Panigada, A.1
Galton, I.2
-
15
-
-
72949087592
-
A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction
-
Dec
-
Panigada and I. Galton, "A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction", IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3314-3328, Dec. 2009.
-
(2009)
IEEE J. Solid-state Circuits
, vol.44
, Issue.12
, pp. 3314-3328
-
-
Panigada1
Galton, I.2
-
16
-
-
0028428441
-
Granular quantization noise in a class of delta-sigma modulators
-
May
-
I. Galton, "Granular quantization noise in a class of delta-sigma modulators", IEEE Trans. Inf. Theory, vol. 40, no. 3, pp. 848-859, May 1994.
-
(1994)
IEEE Trans. Inf. Theory
, vol.40
, Issue.3
, pp. 848-859
-
-
Galton, I.1
-
17
-
-
0017542211
-
A necessary and sufficient condition for quantization errors to be uniform and white
-
Oct
-
A. B. Sripad and D. L. Snyder, "A necessary and sufficient condition for quantization errors to be uniform and white", IEEE Trans. Acoust., Speech, Signal Process., vol. ASSP-25, no. 5, pp. 442-448, Oct. 1977.
-
(1977)
IEEE Trans. Acoust., Speech, Signal Process.
, vol.ASSP-25
, Issue.5
, pp. 442-448
-
-
Sripad, A.B.1
Snyder, D.L.2
-
18
-
-
0031704810
-
A 113 dB SNR oversampling DAC with segmented noise-shaped scrambling
-
Feb, 413
-
R. Adams, K. Nguyen, and K. Sweetland, "A 113 dB SNR oversampling DAC with segmented noise-shaped scrambling", in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1998, pp. 62-63, 413.
-
(1998)
IEEE Int. Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers
, pp. 62-63
-
-
Adams, R.1
Nguyen, K.2
Sweetland, K.3
-
19
-
-
0024029371
-
Simulating and testing oversampled analog-to-digital converters
-
Jun
-
B. Boser, K.-P. Karmann, H. Martin, and B. Wooley, "Simulating and testing oversampled analog-to-digital converters", IEEE Trans. Computer-Aided Design, vol. 7, no. 6, pp. 668-674, Jun. 1988.
-
(1988)
IEEE Trans. Computer-aided Design
, vol.7
, Issue.6
, pp. 668-674
-
-
Boser, B.1
Karmann, K.-P.2
Martin, H.3
Wooley, B.4
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