-
1
-
-
9144245616
-
Equalization and clock recovery for a 2.5–10-Gb/s 2-PAM/4-PAM backplane transceiver cell
-
J. L. Zerbe Equalization and clock recovery for a 2.5–10-Gb/s 2-PAM/4-PAM backplane transceiver cell IEEE J. Solid-State Circuits 38 12 2121 2130 Dec. 2003
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.12
, pp. 2121-2130
-
-
Zerbe, J.L.1
-
2
-
-
50949117733
-
Analog multi-tone signaling for high-speed backplane electrical links
-
A. Amirkhany A. Abbasfar V. Stojanovic M. A. Horowitz Analog multi-tone signaling for high-speed backplane electrical links Proc. IEEE Global Telecommun. Conf. Proc. IEEE Global Telecommun. Conf. 2006-Nov.
-
(2006)
-
-
Amirkhany, A.1
Abbasfar, A.2
Stojanovic, V.3
Horowitz, M.A.4
-
3
-
-
39749093751
-
A 24 Gb/s software programmable multi-channel transmitter
-
A. Amirkhany A 24 Gb/s software programmable multi-channel transmitter IEEE Symp. VLSI Circuits Dig. 38 39 IEEE Symp. VLSI Circuits Dig. Kyoto Japan 2007-Jun.
-
(2007)
, pp. 38-39
-
-
Amirkhany, A.1
-
4
-
-
39049085269
-
A 0.36 W 6b up to 20 GS/s DAC for UWB wave formation
-
D. Baranauskas D. Zelenin A 0.36 W 6b up to 20 GS/s DAC for UWB wave formation IEEE ISSCC Dig. Tech. Papers 580 581 IEEE ISSCC Dig. Tech. Papers 2006-Feb.
-
(2006)
, pp. 580-581
-
-
Baranauskas, D.1
Zelenin, D.2
-
5
-
-
28144461878
-
A 22 GS/s 6b DAC with integrated digital ramp generator
-
P. Schvan D. Pollex T. Bellingrath A 22 GS/s 6b DAC with integrated digital ramp generator IEEE ISSCC Dig. Tech. Papers 122 123 IEEE ISSCC Dig. Tech. Papers 2005-Feb.
-
(2005)
, pp. 122-123
-
-
Schvan, P.1
Pollex, D.2
Bellingrath, T.3
-
7
-
-
0032317770
-
A 10-b, 500-MSample/s CMOS DAC in 0.6 mm $^2$
-
C.-K. Lin K. Bult A 10-b, 500-MSample/s CMOS DAC in 0.6 mm $^2$ IEEE J. Solid-State Circuits 33 12 1948 1958 Dec. 1998
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, Issue.12
, pp. 1948-1958
-
-
Lin, C.-K.1
Bult, K.2
-
8
-
-
0346076818
-
Gradient error cancellation and quadratic error reduction in unary and binary D/A converters
-
M. Vadipour Gradient error cancellation and quadratic error reduction in unary and binary D/A converters IEEE Trans. Circuits Syst. II 50 12 1002 1007 Dec. 2003
-
(2003)
IEEE Trans. Circuits Syst. II
, vol.50
, Issue.12
, pp. 1002-1007
-
-
Vadipour, M.1
-
9
-
-
0022862503
-
An 80-MHz 8-bit CMOS D/A converter
-
T. Miki An 80-MHz 8-bit CMOS D/A converter IEEE J. Solid-State Circuits SSC-21 6 983 988 Dec. 1986
-
(1986)
IEEE J. Solid-State Circuits
, vol.SSC-21
, Issue.6
, pp. 983-988
-
-
Miki, T.1
-
10
-
-
39049131196
-
Implications of proximity effects for analog design
-
P. G. Drennan M. L. Kniffin D. R. Locascio Implications of proximity effects for analog design Proc. IEEE CICC 169 176 Proc. IEEE CICC 2006-Sep.
-
(2006)
, pp. 169-176
-
-
Drennan, P.G.1
Kniffin, M.L.2
Locascio, D.R.3
-
11
-
-
33847738887
-
A low-spurious low-power 12-bit 160-MS/s DAC in 90-nm CMOS for baseband wireless transmitter
-
D. Seo G. H. McAllister A low-spurious low-power 12-bit 160-MS/s DAC in 90-nm CMOS for baseband wireless transmitter IEEE J. Solid-State Circuits 42 3 486 495 Mar. 2007
-
(2007)
IEEE J. Solid-State Circuits
, vol.42
, Issue.3
, pp. 486-495
-
-
Seo, D.1
McAllister, G.H.2
-
12
-
-
42649119327
-
A 130 nm CMOS 6-bit full Nyquist 3 GS/s DAC
-
P. Palmers X. Wu M. Steyaert A 130 nm CMOS 6-bit full Nyquist 3 GS/s DAC IEEE A-SSCC Dig. Tech. Papers 348 351 IEEE A-SSCC Dig. Tech. Papers 2007-Nov.
-
(2007)
, pp. 348-351
-
-
Palmers, P.1
Wu, X.2
Steyaert, M.3
-
13
-
-
34547288616
-
A 16b 400ms/s DAC with $<{-}$80dbc IMD to 300MHz and $<{-}$ 160dBm/Hz noise power spectral density
-
CA
-
W. Schofield D. Mercer L. S. Onge A 16b 400ms/s DAC with $<{-}$80dbc IMD to 300MHz and $<{-}$ 160dBm/Hz noise power spectral density IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers 1 126 482 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers San Francisco CA 2003-Feb.
-
(2003)
, vol.1
, pp. 126-482
-
-
Schofield, W.1
Mercer, D.2
Onge, L.S.3
-
14
-
-
0010157943
-
Design of Integrated Circuits For Optical Communications
-
McGraw-Hill New York
-
Design of Integrated Circuits For Optical Communications 2002 McGraw-Hill New York
-
(2002)
-
-
-
15
-
-
4344581248
-
10 Gb/s limiting amplifier and laser/modulator driver in 0.18 um CMOS technology
-
S. Galal B. Razavi 10 Gb/s limiting amplifier and laser/modulator driver in 0.18 um CMOS technology IEEE ISSCC Dig. Tech. Papers 188 189 IEEE ISSCC Dig. Tech. Papers 2003-Feb.
-
(2003)
, pp. 188-189
-
-
Galal, S.1
Razavi, B.2
-
16
-
-
85177128229
-
A new technique for characterization of digital-to-analog converters in high-speed systems
-
J. Savoj A. Abbasfar A. Amirkhany B. W. Garlepp M. A. Horowitz A new technique for characterization of digital-to-analog converters in high-speed systems Proc. Design, Autom. & Test Eur. Proc. Design, Autom. & Test Eur. 2007-Apr.
-
(2007)
-
-
Savoj, J.1
Abbasfar, A.2
Amirkhany, A.3
Garlepp, B.W.4
Horowitz, M.A.5
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