Nested digital background calibration of a 12-bit pipelined ADC without an input SHA

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 10, 2009, Pages 2780-2789

  Wang, Haoyue ^a   Wang, Xiaoyue ^b   Hurst, Paul J ^c   Lewis, Stephen H ^c  

^a Atheros Communications Inc   (China)

^b MARVELL SEMICONDUCTOR INC   (United States)

^c Davis   (United States)

Author keywords

Analog to digital conversion; CMOS analog integrated circuits; Digital background calibration; Nested calibration

Indexed keywords

ADAPTIVE INTERPOLATORS; ALGORITHMIC ADC; CMOS ANALOG INTEGRATED CIRCUITS; DIFFERENTIATORS; DIGITAL BACKGROUND; DIGITAL BACKGROUND CALIBRATION; INPUT SAMPLE; INTEGRAL NONLINEARITY; LEAST SIGNIFICANT BITS; NESTED CALIBRATION; PIPELINED ADCS; PIPELINED ANALOG-TO-DIGITAL CONVERTER; POWER DISSIPATION; SIGNAL TO NOISE AND DISTORTION RATIO; SINUSOIDAL INPUT; SPURIOUS-FREE DYNAMIC RANGE;

ANALOG CIRCUITS; CALIBRATION; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; LINEAR INTEGRATED CIRCUITS; MULTICARRIER MODULATION; TIME MEASUREMENT; TIME VARYING SYSTEMS;

ANALOG TO DIGITAL CONVERSION;

EID: 70350596356     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2028756     Document Type: Article

References (36)

1. H.-S. Lee, D. A. Hodges, and P. R. Gray, "A self-calibrating 15 bit CMOS A/D converter," IEEE J. Solid-State Circuits, vol.SSC-19, no.6, pp. 813-819, Dec. 1984.
2. P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, "A ratio-independent algorithmic analog-to-digital conversion technique," IEEE J. Solid-State Circuits, vol.SSC-19, no.6, pp. 828-836, Dec. 1984.
3. C.-C. Shih and P. R. Gray, "Reference refreshing cyclic analog-to-digital and digital-to-analog converters," IEEE J. Solid-State Circuits, vol.SSC-21, pp. 544-554, Apr. 1986.
4. B.-S. Song, M. F. Tompsett, and K. R. Lakshmikumar, "A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter," IEEE J. Solid-State Circuits, vol.SSC-23, pp. 1324-1333, Dec. 1988.
5. Y.-M. Lin, B. Kim, and P. R. Gray, "A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mCMOS," IEEE J. Solid-State Circuits, vol.26, no.4, pp. 628-636, Apr. 1991.
6. S.-H. Lee and B.-S. Song, "Digital-domain calibration of multistep analog-to-digital converters," IEEE J. Solid-State Circuits, vol.27, no.12, pp. 1679-1688, Dec. 1992.
7. A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, vol.28, no.12, pp. 1207-1215, Dec. 1993.
8. H.-S. Lee, "A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC," IEEE J. Solid-State Circuits, vol.29, no.4, pp. 509-515, Apr. 1994.
9. S.-U. Kwak, B.-S. Song, and K. L. Bacrania, "A 15-b 5-Msample/s low-spurious CMOS ADC," IEEE J. Solid-State Circuits, vol.32, no.12, pp. 1866-1875, Dec. 1997.
10. J. M. Ingino and B. A. Wooley, "A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter," IEEE J. Solid-State Circuits, vol.33, no.12, pp. 1920-1931, Dec. 1998.
11. O. E. Erdǒgan, P. J. Hurst, and S. H. Lewis, "A 12-b digital-background- calibrated algorithmic ADC with-90-dB THD," IEEE J. Solid-State Circuits, vol.34, no.12, pp. 1812-1820, Dec. 1999.
12. J. Ming and S. H. Lewis, "An 8-bit 80-Msample/s pipelined analog-todigital converter with background calibration," IEEE J. Solid-State Circuits, vol.36, no.10, pp. 1489-1497, Oct. 2001.
13. E. B. Blecker, T. M. McDonald, O. E. Erdǒgan, P. J. Hurst, and S. H. Lewis, "Digital background calibration of an algorithmic analog-todigital converter using a simplified queue," IEEE J. Solid-State Circuits, vol.38, no.6, pp. 1059-1062, Jun. 2003.
14. J. Li and U. Moon, "Background calibration techniques for multistage pipelined ADCs with digital redundancy," IEEE Trans. Circuits Syst. II, vol.23, no.9, pp. 531-538, Sep. 2003.
15. X. Wang, "Nested digital background calibration of pipelined analog-to-digital converters," Ph.D. dissertation, University of California, Davis, 2003.
16. B. Murmann and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE J. Solid-State Circuits, vol.38, no.12, pp. 2040-2050, Dec. 2003.
17. Y. Chiu, C. W. Tsang, B. Nikolić, and P. R. Gray, "Least mean square adaptive digital background calibration of pipelined analog-to-digital converters," IEEE Trans. Circuits Syst. I, vol.51, no.1, pp. 38-46, Jan. 2004.
18. X. Wang, P. J. Hurst, and S. H. Lewis, "A 12-bit, 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration," IEEE J. Solid-State Circuits, vol.39, no.11, pp. 1799-1808, Nov. 2004.
19. J. P. Keane, P. J. Hurst, and S. H. Lewis, "Background interstage gain calibration technique for pipelined ADCs," IEEE Trans. Circuits Syst. I, vol.52, no.1, pp. 32-43, Jan. 2005.
20. J. Li, G. Ahn, D. Chang, and U. Moon, "A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR," IEEE J. Solid-State Circuits, vol.40, no.4, pp. 960-969, Apr. 2005.
21. C. R. Grace, P. J. Hurst, and S. H. Lewis, "A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration," IEEE J. Solid- State Circuits, vol.40, no.5, pp. 1038-1046, May 2005.
22. J. McNeill, M. C. W. Coln, and B. J. Larivee, ""Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC," IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2437-2444, Dec. 2005.
23. J. P. Keane, P. J. Hurst, and S. H. Lewis, "Digital background calibration for memory effects in pipelined analog-to-digital converters," IEEE Trans. Circuits Syst. I, vol.53, no.3, pp. 511-525, Mar. 2006.
24. L. A. Singer and T. L. Brooks, "A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter," in Proc. Symp. VLSI Circuits, Jun. 1996, pp. 94-95.
25. A. M. A. Ali, C. Dillon, R. Sneed, A. S. Morgan, S. Bardsley, J. Kornblum, and L. Wu, "A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter," IEEE J. Solid-State Circuits, vol.41, no.8, pp. 1846-1855, Aug. 2006.
26. T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35mWpipeline A/D converter," IEEE J. Solid-State Circuits, vol.30, no.3, pp. 166-172, Mar. 1995.
27. T. B. Cho, D. W. Cline, C. S. G. Conroy, and P. R. Gray, "Design considerations for low-power, high-speed CMOS analog/digital converters," in Proc. IEEE Symp. Low Power Electronics, Oct. 1994, pp. 70-73.
28. D. W. Cline and P. R. Gray, "A power optimized 13-b 5 MSamples/s pipelined analog-to-digital converter in-mCMOS," IEEE J. Solid- State Circuits, vol.31, no.3, pp. 294-303, Mar. 1996.
29. I. Galton, "Digital cancellation of D/A converter noise in pipelined A/D converters," IEEE Trans. Circuits Syst. II, vol.47, no.3, pp. 185-196, Mar. 2000.
30. C. W. Farrow, "A continuously variable digital delay element," in Proc. IEEE Int. Symp. Circuits and Systems, Jun. 1988, vol.3, pp. 2641-2645.
31. T. I. Laakso, V. Välimäki, M. Karjalainen, and U. K. Laine, "Splitting the unit delay-Tools for fractional delay filter design," IEEE Signal Process. Mag., vol.13, no.1, pp. 30-60, Jan. 1996.
32. S. M. Jamal, D. Fu, M. P. Singh, P. J. Hurst, and S. H. Lewis, "Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter," IEEE Trans. Circuits Syst. I, vol.51, no.1, pp. 130-139, Jan. 2004.
33. B. Widrow and S. D. Stearns, Adaptive Signal Processing. Upper Saddle River, NJ: Prentice-Hall, 1985.
34. S. Haykin, Adaptive Filter Design, 3rd ed. Upper Saddle River, NJ: Prentice-Hall, 1996.
35. S. Huang and B. C. Levy, "Adaptive blind calibration of timing offset and gain mismatch for two-channel time-interleaved ADCs," IEEE Trans. Circuits Syst. I, vol.53, no.6, pp. 1278-1288, Jun. 2006.
36. A. V. Oppenheim, R. W. Schafer, and J. R. Buck, Discrete-Time Signal Processing, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 1999.