A 16-bit 250-MS/s if sampling pipelined ADC with background calibration

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 12, 2010, Pages 2602-2612

  Ali, Ahmed M A ^a   Morgan, Andrew Andy ^a   Dillon, Christopher ^a   Patterson, Greg ^a   Puckett, Scott ^a   Bhoraskar, Paritosh ^a   Dinc, Huseyin ^a   Hensley, Mike ^a   Stop, Russell ^a   Bardsley, Scott ^a   Lattimore, David ^a   Bray, Jeff ^a   Speir, Carroll ^a   Sneed, Robert ^a  

^a ANALOG DEVICES INC   (United States)

Author keywords

A D converter (ADC); background calibration; buffer; IF sampling; pipeline; sample and hold amplifier (SHA) less

Indexed keywords

A/D CONVERTER; BACKGROUND CALIBRATION; BUFFER; IF SAMPLING; SAMPLE-AND-HOLD AMPLIFIER;

ANALOG TO DIGITAL CONVERSION;

CALIBRATION;

EID: 78650071419     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2073194     Document Type: Conference Paper

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