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Volumn 39, Issue 7, 2004, Pages 1056-1063

A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution

Author keywords

Analog digital conversion; Continuous time filters; Delta sigma modulation; Low pass filters; Low voltage design; Sigma delta modulation

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; DELTA SIGMA MODULATION; ELECTRIC POTENTIAL; ENERGY DISSIPATION; LOW PASS FILTERS; OPTICAL RESOLVING POWER; WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 3042737899     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.829925     Document Type: Conference Paper
Times cited : (144)

References (13)
  • 2
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    • A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture
    • Feb.
    • D. Miyazaki, S. Kawahito, and M. Furuta, "A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture," IEEE J. Solid-State Circuits, vol. 38, pp. 369-373, Feb. 2003.
    • (2003) IEEE J. Solid-state Circuits , vol.38 , pp. 369-373
    • Miyazaki, D.1    Kawahito, S.2    Furuta, M.3
  • 3
    • 0033872609 scopus 로고    scopus 로고
    • A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC
    • Mar.
    • I. Mehr and L. Singer, "A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC," IEEE J. Solid-State Circuits, vol. 35, pp. 318-325, Mar. 2000.
    • (2000) IEEE J. Solid-state Circuits , vol.35 , pp. 318-325
    • Mehr, I.1    Singer, L.2
  • 4
    • 0034479805 scopus 로고    scopus 로고
    • A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8 × oversampling ratio
    • Dec.
    • I. Fujimori et al., "A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8 × oversampling ratio," IEEE J. Solid-State Circuits, vol. 35, pp. 1820-1828, Dec. 2000.
    • (2000) IEEE J. Solid-state Circuits , vol.35 , pp. 1820-1828
    • Fujimori, I.1
  • 5
    • 0034478801 scopus 로고    scopus 로고
    • A high-performance multibit delta sigma CMOS ADC
    • Dec.
    • Y. Geerts, M. S. J. Steyaert, and W. Sansen, "A high-performance multibit delta sigma CMOS ADC," IEEE J. Solid-State Circuits, vol. 35, pp. 1829-1840, Dec. 2000.
    • (2000) IEEE J. Solid-state Circuits , vol.35 , pp. 1829-1840
    • Geerts, Y.1    Steyaert, M.S.J.2    Sansen, W.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.