A 14-b 100-MS/s pipelined ADC with a merged SHA and first MDAC

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 12, 2008, Pages 2613-2619

  Lee, Byung Geun ^a   Min, Byung Moo ^b   Manganaro, Gabriele ^b   Valvano, Jonathan W ^c  

^a QUALCOMM INC   (United States)

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^c The University of Texas at Austin   (United States)

Author keywords

Analog to digital conversion (ADC); Capacitor sharing; High speed; Low power; Opamp sharing; Pipelined analog to digital converter (ADC); Small area

Indexed keywords

CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; DIELECTRIC DEVICES; DIGITAL SIGNAL PROCESSING; DIGITAL TO ANALOG CONVERSION; ELECTRIC EQUIPMENT; FREQUENCY CONVERTERS; HYBRID COMPUTERS; MULTICARRIER MODULATION; OPERATIONAL AMPLIFIERS; PIPELINES;

ANALOG-TO-DIGITAL CONVERSION (ADC); HIGH SPEED; LOW POWER; OPAMP-SHARING; PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC); SMALL AREA;

ANALOG TO DIGITAL CONVERSION;

EID: 57849165939     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2006309     Document Type: Conference Paper

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