A 12-Bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 11, 2004, Pages 1799-1808

  Wang, Xiaoyue ^a,b   Hurst, Paul J ^c   Lewis, Stephen H ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b MARVELL SEMICONDUCTOR INC   (United States)

^c University of California   (United States)

Author keywords

Analog to digital conversion; CMOS analog integrated circuits; Digital background calibration; Nested calibration

Indexed keywords

ALGORITHMS; CALIBRATION; CMOS INTEGRATED CIRCUITS; OPERATIONAL AMPLIFIERS; SIGNAL TO NOISE RATIO; SOFTWARE PROTOTYPING;

DIGITAL BACKGROUND CALIBRATION; INPUT GAIN ERROR; NESTED CALIBRATION; QUANTIZATION ERROR;

ANALOG TO DIGITAL CONVERSION;

EID: 8344221254     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.835826     Document Type: Article

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