A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 11, 2004, Pages 1829-1838

  Manganaro, Gabriele ^a,b   Kwak, Sung Ung ^a,c   Bugeja, Alexander R ^a  

^a Engim Inc   (United States)

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^c Silicon Laboratories   (United States)

Author keywords

Analog integrated circuits; BiCMOS analog integrated circuits; Data conversion; Delay locked loops; Digital analog conversion; Integrated circuit design

Indexed keywords

BROADBAND NETWORKS; CAPACITORS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOCAL AREA NETWORKS; SWITCHING; TRANSISTORS;

BICMOS ANALOG INTEGRATED CIRCUITS; DATA CONVERSION; DELAY LOCKED LOOPS; INTEGRATED CIRCUIT DESIGN;

DIGITAL TO ANALOG CONVERSION;

EID: 8344250999     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.835829     Document Type: Article

References (12)

1. F.-J. Wang, G. C. Temes, and S. Law, "A quasipassive CMOS pipeline D/A converter," IEEE J. Solid-State Circuits, vol. 24, pp. 1752-1755, Dec. 1989.
2. K. Khanoyan, F. Behbahani, and A. Abidi, "A 10-b, 400 MS/s glitch-free CMOS D/A converter," in Proc. IEEE Int. Symp. VLSI Circuits, 1999, pp. 73-76.
3. A. Rofougaran, G. Chang, J. J. Rael, J. Y.-C. Chang, M. Rofougaran, P. J. Chang, M. Djafari, M.-K. Ku, E. W. Roth, A. Abidi, and H. Samueli, "A single-chip 900-MHz spread-spectrum wireless transceiver in 1 μm CMOS-Part I: Architecture and transmitter design," IEEE J. Solid-State Circuits, vol. 33, pp. 515-533, Apr. 1998.
4. R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing. New York: Wiley, 1986.
5. D. A. Johns and K. Martin, Analog Integrated Circuits Design. New York: Wiley, 1997.
6. B. Razavi and J. J. Sung, "A 6 GHz 60 mW BiCMOS phase-locked loop," IEEE J. Solid-State Circuits, vol. 29, pp. 1560-1565, Dec. 1994.
7. P. E. Allen, "A model for slew-induced distortion in single-amplifier active filters," IEEE Trans. Circuits Syst., vol. CAS-25, pp. 565-572, Aug. 1978.
8. E. Sánchez-Sinencio and M. L. Majewski, "A nonlinear macromodel of operational amplifiers in the frequency domain," IEEE Trans. Circuits Syst., vol. CAS-26, pp. 395-402, June 1979.
9. W. M. C. Sansen, H. Qiuting, and K. A. I. Halonen, "Transient analysis of charge transfer in SC filters-Gain error and distortion," IEEE J. Solid-State Circuits, vol. SC-22, pp. 268-276, Apr. 1987.
10. B. Razavi, "Design of monolithic phase-locked loops and clock recovery circuits-A tutorial," in Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design, B. Razavi, Ed. New York: IEEE Press, 1996.
11. _, Principles of Data Conversion System Design. New York: IEEE Press, 1995.
12. 2," IEEE J. Solid-State Circuits, vol. 33, pp. 1948-1958, Dec. 1998.