A 40GS/s 6b ADC in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 390-391

  Greshishchev, Yuriy M ^a   Aguirre, Jeorge ^a   Besson, Marinette ^a   Gibbins, Robert ^a   Falt, Chris ^a   Flemke, Philip ^a   Ben Hamida, Naim ^a   Pollex, Daniel ^a   Schvan, Peter ^a   Wang, Shing Chi ^a  

^a NORTEL NETWORKS   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

40 GB/S; DUAL-POLARIZATIONS; GIGAHERTZ RANGE; INPUT FREQUENCY; JITTER PERFORMANCE; MODULATED CHANNELS; ON CHIPS; OPTICAL FREQUENCY; POWER DISSIPATION; PRACTICAL SOLUTIONS; PRODUCTION TESTING; SAMPLING JITTER; SAMPLING RATES; SINUSOIDAL SIGNALS; TEST SIGNAL; TIMING ERRORS; TIMING MISMATCH;

FREQUENCY ALLOCATION; FREQUENCY DIVISION MULTIPLEXING; LIGHT TRANSMISSION; QUADRATURE PHASE SHIFT KEYING; TIME MEASUREMENT; TIMING CIRCUITS;

JITTER;

EID: 77952200522     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433972     Document Type: Conference Paper

References (6)

1. Kim Roberts, "Real Time 40 Gb/s Coherent System," in Coherent Optical Technologies and Applications, (Optical Society of America, 2008), paper CWC1.
2. Peter Schvan, Jerome Bach, Chris Falt, Philip Flemke, Yuriy Greshishchev, Naim Ben-Hamida, Daniel Pollex, John Sitch, Shing-Chi Wang, John Wolczanski, "A 24GS/s 6b ADC in 90nm CMOS", ISSCC Dig. Tech. Papers, pp. 544-545, Feb. 2008.
3. O. Agazzi, D. Crivelli, M. Hueda, et al., "A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion Compensation of Multi-mode Optical Fibers at 10Gb/s," ISSCC Dig. Tech. Papers, pp. 232-233, Feb., 2008.
4. June Cao, Bo Zhang, Ullas Singh, et al.," A 500mW Digitally Calibrated AFE in 65nm CMOS for 10Gb/s Serial Links over Backplane and Multimode Fiber", ISSCC Dig. Tech. Papers, pp. 370-371, Feb., 2009.
5. Ciciero S. Voucher, Igor Ferencic, Matthias Locher, et al. " A family of Low-Power-Truly Modular Programmable Dividers in Standard 0.35um CMOS technology", IEEE J. Solid-State Circuits, vol.35,no.7, pp.1039-1045.
6. IEEE Standard 1241-2000 and Draft P1057/D7.6.