-
3
-
-
0028518013
-
A 16 bit D/A converter with increased spurious free dynamic range
-
Oct.
-
D. Mercer, "A 16 bit D/A converter with increased spurious free dynamic range," IEEE J. Solid-State Circuits, vol. 29, pp. 1180-1185, Oct. 1994.
-
(1994)
IEEE J. Solid-state Circuits
, vol.29
, pp. 1180-1185
-
-
Mercer, D.1
-
4
-
-
0032316466
-
A 12 bit intrinsic accuracy high speed CMOS DAC
-
Dec.
-
J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 12 bit intrinsic accuracy high speed CMOS DAC," IEEE J. Solid-State Circuits, vol. 33, pp. 1959-1969, Dec. 1998.
-
(1998)
IEEE J. Solid-state Circuits
, vol.33
, pp. 1959-1969
-
-
Bastos, J.1
Marques, A.M.2
Steyaert, M.S.J.3
Sansen, W.4
-
6
-
-
0031233794
-
A low glitch 14 bit 100 MHz D/A converter
-
Sept.
-
B. Tesch and J. Garcia, "A low glitch 14 bit 100 MHz D/A converter," IEEE J. Solid-State Circuits, vol. 32, pp. 1465-1469, Sept. 1997.
-
(1997)
IEEE J. Solid-state Circuits
, vol.32
, pp. 1465-1469
-
-
Tesch, B.1
Garcia, J.2
-
7
-
-
0001264767
-
2 random walk CMOS DAC
-
2 random walk CMOS DAC," in ISSCC Dig. Tech. Papers, 1999, pp. 146-147.
-
(1999)
ISSCC Dig. Tech. Papers
, pp. 146-147
-
-
Vandenbussche, J.1
Van Der Plas, G.2
Van Den Bosch, A.3
Daems, W.4
Gielen, G.5
Steyaert, M.S.J.6
Sansen, W.7
-
8
-
-
0005191097
-
CODEC for echo-canceling, full-rate ADSL modems
-
R. Hester, S. Mukherjee, D. Padgett, D. Richardson, W. Bright, M. Sarraj, M. Agah, A. Bellaouai, I. Chaudry, J. Hellums, K. Islam, A. Loloee, J. Nabicht, F. Tsay, and G. Westphal, "CODEC for echo-canceling, full-rate ADSL modems," in ISSCC Dig. Tech. Papers, 1999, pp. 242-243.
-
(1999)
ISSCC Dig. Tech. Papers
, pp. 242-243
-
-
Hester, R.1
Mukherjee, S.2
Padgett, D.3
Richardson, D.4
Bright, W.5
Sarraj, M.6
Agah, M.7
Bellaouai, A.8
Chaudry, I.9
Hellums, J.10
Islam, K.11
Loloee, A.12
Nabicht, J.13
Tsay, F.14
Westphal, G.15
-
9
-
-
0024898312
-
A self-calibration technique for monolithic high-resolution D/A converters
-
Dec.
-
D. W. J. Groeneveld, H. J. Schouwenaars, H. A. H. Termeer, and C. A. A. Bastiaansen, "A self-calibration technique for monolithic high-resolution D/A converters," IEEE J. Solid-State Circuits, vol. 24, pp. 1517-1522, Dec. 1989.
-
(1989)
IEEE J. Solid-state Circuits
, vol.24
, pp. 1517-1522
-
-
Groeneveld, D.W.J.1
Schouwenaars, H.J.2
Termeer, H.A.H.3
Bastiaansen, C.A.A.4
-
10
-
-
0005245192
-
A 25 kft 768 kb/s CMOS transceiver for multiple bit-rate DSL
-
M. Moyal, M. Groepl, and T. Blon, "A 25 kft 768 kb/s CMOS transceiver for multiple bit-rate DSL," in ISCC Dig. Tech. Papers, 1999, pp. 244-2456.
-
(1999)
ISCC Dig. Tech. Papers
, pp. 244-2456
-
-
Moyal, M.1
Groepl, M.2
Blon, T.3
-
11
-
-
0031193193
-
Specifying communications DAC's
-
July
-
P. Hendriks, "Specifying communications DAC's," IEEE Spectrum, vol. 34, pp. 58-69, July 1997.
-
(1997)
IEEE Spectrum
, vol.34
, pp. 58-69
-
-
Hendriks, P.1
-
12
-
-
0342624835
-
Transient analysis of switched current source
-
Mar.
-
T. Miki, Y. Nakamura, K. Okada, and Y. Horiba, "Transient analysis of switched current source," IEICE Trans. Electron., vol. E75-C, pp. 288-296, Mar. 1992.
-
(1992)
IEICE Trans. Electron.
, vol.E75-C
, pp. 288-296
-
-
Miki, T.1
Nakamura, Y.2
Okada, K.3
Horiba, Y.4
-
13
-
-
0024754187
-
Matching properties of MOS transistors
-
Oct.
-
M. Pelgrom, A. Duinmaijer, and A. Webers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, Oct. 1989.
-
(1989)
IEEE J. Solid-state Circuits
, vol.24
, pp. 1433-1440
-
-
Pelgrom, M.1
Duinmaijer, A.2
Webers, A.3
-
14
-
-
0030701047
-
Custom analog low power design: The problem of low voltage and mismatch
-
M. S. J. Steyaert, V. Peluso, J. Bastos, P. Kinget, and W. Sansen, "Custom analog low power design: The problem of low voltage and mismatch," in Proc. IEEE Custom Integrated Circuit Conf., 1997, pp. 285-292.
-
(1997)
Proc. IEEE Custom Integrated Circuit Conf.
, pp. 285-292
-
-
Steyaert, M.S.J.1
Peluso, V.2
Bastos, J.3
Kinget, P.4
Sansen, W.5
-
15
-
-
0033280130
-
A 10b, 400 MS/s glitch-free CMOS D/A converter
-
paper 8-1
-
K. Khanoyan, F. Behbahani, and A. Abidi, "A 10b, 400 MS/s glitch-free CMOS D/A converter," in 1999 Symp. VLSI Circuits Dig. Tech. Papers, paper 8-1.
-
1999 Symp. VLSI Circuits Dig. Tech. Papers
-
-
Khanoyan, K.1
Behbahani, F.2
Abidi, A.3
-
16
-
-
0026898371
-
Fully bipolar 120 MS/s 10 bit track and hold circuit
-
July
-
P. Vorenkamp and J. Verdaasdonk, "Fully bipolar 120 MS/s 10 bit track and hold circuit," IEEE J. Solid-State Circuits, vol. 27. pp. 988-992. July 1992.
-
(1992)
IEEE J. Solid-state Circuits
, vol.27
, pp. 988-992
-
-
Vorenkamp, P.1
Verdaasdonk, J.2
-
17
-
-
0031378861
-
A 12 bit 60 MS/s cascaded folding and interpolating ADC
-
Dec.
-
P. Vorenkamp and R. Roovers, "A 12 bit 60 MS/s cascaded folding and interpolating ADC," IEEE J. Solid-State Circuits, vol. 33, pp. 1876-1886, Dec. 1997.
-
(1997)
IEEE J. Solid-state Circuits
, vol.33
, pp. 1876-1886
-
-
Vorenkamp, P.1
Roovers, R.2
-
18
-
-
0026138527
-
A high-speed sample-and-hold technique using a Miller hold capacitance
-
Apr.
-
P. Lim and B. Wooley, "A high-speed sample-and-hold technique using a Miller hold capacitance," IEEE J. Solid-State Circuits, vol. 26, pp. 643-651, Apr. 1991.
-
(1991)
IEEE J. Solid-state Circuits
, vol.26
, pp. 643-651
-
-
Lim, P.1
Wooley, B.2
-
19
-
-
0026220879
-
A 200-MHz CMOS x/ sin(x) digital filter for compensating D/A converter frequency response disrortion
-
Sept.
-
T. Lin and H. Samueli, "A 200-MHz CMOS x/ sin(x) digital filter for compensating D/A converter frequency response disrortion," IEEE J. Solid-State Circuits, vol. 26, pp. 1278-1285, Sept. 1991.
-
(1991)
IEEE J. Solid-state Circuits
, vol.26
, pp. 1278-1285
-
-
Lin, T.1
Samueli, H.2
-
20
-
-
0343059061
-
-
Datasheet, Analog Devices, Inc., Wilmington, MA
-
"14-bit, 100MSPS+ TxDAC D/A converter," Datasheet, Analog Devices, Inc., Wilmington, MA, 1998.
-
(1998)
14-bit, 100MSPS+ TxDAC D/A Converter
-
-
|