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Volumn 34, Issue 12, 1999, Pages 1719-1732

14-b, 100-MS/s CMOS DAC designed for spectral performance

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL TO ANALOG CONVERSION; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; HARMONIC ANALYSIS; INTEGRATED CIRCUIT LAYOUT; SIGNAL DISTORTION; WAVEFORM ANALYSIS;

EID: 0033281056     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.808897     Document Type: Article
Times cited : (79)

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  • 6
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    • Sept.
    • B. Tesch and J. Garcia, "A low glitch 14 bit 100 MHz D/A converter," IEEE J. Solid-State Circuits, vol. 32, pp. 1465-1469, Sept. 1997.
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  • 10
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    • A 25 kft 768 kb/s CMOS transceiver for multiple bit-rate DSL
    • M. Moyal, M. Groepl, and T. Blon, "A 25 kft 768 kb/s CMOS transceiver for multiple bit-rate DSL," in ISCC Dig. Tech. Papers, 1999, pp. 244-2456.
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    • Moyal, M.1    Groepl, M.2    Blon, T.3
  • 11
    • 0031193193 scopus 로고    scopus 로고
    • Specifying communications DAC's
    • July
    • P. Hendriks, "Specifying communications DAC's," IEEE Spectrum, vol. 34, pp. 58-69, July 1997.
    • (1997) IEEE Spectrum , vol.34 , pp. 58-69
    • Hendriks, P.1
  • 12
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    • Transient analysis of switched current source
    • Mar.
    • T. Miki, Y. Nakamura, K. Okada, and Y. Horiba, "Transient analysis of switched current source," IEICE Trans. Electron., vol. E75-C, pp. 288-296, Mar. 1992.
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    • Miki, T.1    Nakamura, Y.2    Okada, K.3    Horiba, Y.4
  • 16
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    • Fully bipolar 120 MS/s 10 bit track and hold circuit
    • July
    • P. Vorenkamp and J. Verdaasdonk, "Fully bipolar 120 MS/s 10 bit track and hold circuit," IEEE J. Solid-State Circuits, vol. 27. pp. 988-992. July 1992.
    • (1992) IEEE J. Solid-state Circuits , vol.27 , pp. 988-992
    • Vorenkamp, P.1    Verdaasdonk, J.2
  • 17
    • 0031378861 scopus 로고    scopus 로고
    • A 12 bit 60 MS/s cascaded folding and interpolating ADC
    • Dec.
    • P. Vorenkamp and R. Roovers, "A 12 bit 60 MS/s cascaded folding and interpolating ADC," IEEE J. Solid-State Circuits, vol. 33, pp. 1876-1886, Dec. 1997.
    • (1997) IEEE J. Solid-state Circuits , vol.33 , pp. 1876-1886
    • Vorenkamp, P.1    Roovers, R.2
  • 18
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    • A high-speed sample-and-hold technique using a Miller hold capacitance
    • Apr.
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  • 19
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    • T. Lin and H. Samueli, "A 200-MHz CMOS x/ sin(x) digital filter for compensating D/A converter frequency response disrortion," IEEE J. Solid-State Circuits, vol. 26, pp. 1278-1285, Sept. 1991.
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  • 20
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    • Datasheet, Analog Devices, Inc., Wilmington, MA
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.