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Volumn 49, Issue 11, 2002, Pages 712-720

High-speed ΣΔ modulators with reduced timing jitter sensitivity

Author keywords

Amplitude noise; Analog to digital converters (ADCs); Dock jitter; Phase noise; Pulse shaping; Sigma delta modulators ( Ms); Timing jitter

Indexed keywords

DIGITAL TO ANALOG CONVERSION; PULSE SHAPING CIRCUITS; SIGNAL TO NOISE RATIO; TIMING JITTER;

EID: 0036881876     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2002.807575     Document Type: Article
Times cited : (59)

References (8)
  • 2
    • 0032632072 scopus 로고    scopus 로고
    • Analog-to-digital converter survey and analysis
    • Apr.
    • R. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Select. Areas Commun., vol. 17, pp. 539-550, Apr. 1999.
    • (1999) IEEE J. Select. Areas Commun. , vol.17 , pp. 539-550
    • Walden, R.1
  • 4
    • 0033310595 scopus 로고    scopus 로고
    • Analysis of timing jitter in bandpass sigma-delta modulators
    • Aug.
    • H. Tao, L. Toth, and J. Khoury, "Analysis of timing jitter in bandpass sigma-delta modulators," IEEE Trans. Circuits Syst. II, vol. 46, pp. 991-1001, Aug. 1999.
    • (1999) IEEE Trans. Circuits Syst. II , vol.46 , pp. 991-1001
    • Tao, H.1    Toth, L.2    Khoury, J.3
  • 5
    • 0032308948 scopus 로고    scopus 로고
    • A 113-dB SNR oversampled DAC with segmented noise-shaped scrambling
    • Dec.
    • R. Adams, K. Nguyen, and K. Sweetland, "A 113-dB SNR oversampled DAC with segmented noise-shaped scrambling," IEEE J. Solid-State Circuits, vol. 12, pp. 1871-1878, Dec. 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.12 , pp. 1871-1878
    • Adams, R.1    Nguyen, K.2    Sweetland, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.