A background self-calibrated 6b 2.7 GS/s ADC with cascade-calibrated folding-interpolating architecture

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 4, 2010, Pages 707-718

  Nakajima, Yuji ^a   Sakaguchi, Akemi ^b   Ohkido, Toshio ^b   Kato, Norihito ^a   Matsumoto, Tetsuya ^a   Yotsuyanagi, Michio ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b NEC IC Microcomputer Systems Ltd   (Japan)

Author keywords

ADC; Analog to digital conversion; Background; Calibration; Digital smoothing; Folding; Interpolation; Low power

Indexed keywords

90NM CMOS; ADC; ANALOG POWER; BACKGROUND SELF-CALIBRATION; CALIBRATION TECHNIQUES; CONTROL CIRCUITS; DIGITAL BACKGROUND; ENVIRONMENTAL FACTORS; FIGURE OF MERIT; HIGH-SPEED OPERATION; KEY TECHNIQUES; LOW POWER; LOW-POWER CONSUMPTION; ON CHIPS; POWER DISSIPATION; POWER SUPPLY; SMALL DEVICES; SMOOTHING TECHNIQUES; TWO-CHANNEL;

ANALOG TO DIGITAL CONVERSION; CALIBRATION; CMOS INTEGRATED CIRCUITS; DIGITAL DEVICES; INTERPOLATION; TIME VARYING SYSTEMS;

MULTICARRIER MODULATION;

EID: 77950252888     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2042249     Document Type: Article

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