SCOPUS 정보 검색 플랫폼

ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference

Volumn , Issue , 2004, Pages 163-166

Low-power 14-bit current steering D AC, for ADSL2+/CO applications in 0.13μm CMOS

(5) Giotta, Dario a Pessl, Peter a Clara, Martin a Klatzer, Wolfgang a Gaggl, Richard a

a INFINEON TECHNOLOGIES AUSTRIA AG (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA TRANSFER; DIGITAL CIRCUITS; ELECTRIC CURRENTS; ELECTRIC IMPEDANCE; JITTER; OPTIMIZATION; ROBUSTNESS (CONTROL SYSTEMS); SIGNAL PROCESSING; STANDARDS;

DIGITAL SUBSCRIBER LINE (DSL); MULTI-TONE POWER RATIO (MTPR); POWER OPTIMIZATION; TRANSIMPEDANCE;

DIGITAL TO ANALOG CONVERSION;

EID: 17644397580 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (24)

References (9)

1
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- John Wiley & Sons, Inc., Chapter 11, Data Converter Fundamentals; Chapter 12, Thermometer Code Converters; Chapter 14, Oversampling Converters
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- Johns, D.A.¹ Martin, K.²

2
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- T.R. Smith, "Current steering topologies guide D/A converter design", URL: http://www.planetanalog.com/story/OEG20020918S0050
- Current Steering Topologies Guide D/A Converter Design
- Smith, T.R.¹

3
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- Baird, R.T.¹ Fiez, T.S.²

4
- 0036642106
- An ADSL-RT full-rate analog front end IC with integrated line driver
- July
- H. Weinberger, A. Wiesbauer, et al., "An ADSL-RT Full-Rate Analog Front End IC With Integrated Line Driver", IEEE Journals of Solid-State Circuits, Vol. 37, No. 7, July 2002.
- (2002) IEEE Journals of Solid-state Circuits , vol.37 , Issue.7
- Weinberger, H.¹ Wiesbauer, A.²

5
- 17644412701
- A 12-bit fully differential current-steering DAC with regulated segmented architecture
- M. Clara, A. Wiesbauer, B. Seger, "A 12-Bit Fully Differential Current-Steering DAC with Regulated Segmented Architecture", AustroChip2000, A/D and D/A Section
- AustroChip2000, A/D and D/A Section
- Clara, M.¹ Wiesbauer, A.² Seger, B.³

6
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- A 14-bit, 10-msamples/s D/A converter using multibit ∑Δ modulation
- May
- K. Falakshahi, C. Ken Yang, "A 14-bit, 10-Msamples/s D/A Converter Using Multibit ∑Δ Modulation", IEEE Journals of Solid-State Circuits, Vol. 34, No. 5, May 1999.
- (1999) IEEE Journals of Solid-state Circuits , vol.34 , Issue.5
- Falakshahi, K.¹ Yang, C.K.²

7
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- 2 random walk CMOS DAC
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- 2 Random Walk CMOS DAC", IEEE Journals of Solid-State Circuits, Vol. 34, No. 12, Dec 1999.
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8
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- A 14-bit 1.8V 20-mW 1-mm2 CMOS DAC
- July
- M.P. Tiilikainen, "A 14-bit 1.8V 20-mW 1-mm2 CMOS DAC", IEEE Journals of Solid-State Circuits, Vol. 36, No. 7, July 2001.
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- Tiilikainen, M.P.¹

9
- 0037630997
- A 1.5V 14b 100MS/s self-calibrated DAC
- Y. Cong, R.L. Geiger, "A 1.5V 14b 100MS/s Self-Calibrated DAC", ISSCC 2003, Session 7, Paper 7.2
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- Cong, Y.¹ Geiger, R.L.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.