Analog-to-digital converters: Digitizing the analog world

Proceedings of the IEEE

Volumn 96, Issue 2, 2008, Pages 323-334

  Lee, Hae Seung ^a   Sodini, Charles G ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Analog to digital (A D) converter; Data conversion; Mixed signal

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPARATORS (OPTICAL); DATA HANDLING; DATA STORAGE EQUIPMENT; ELECTRIC SIGNAL SYSTEMS; ENERGY EFFICIENCY; METALS; MIXED SIGNAL INTEGRATED CIRCUITS; MOS DEVICES; OPERATIONAL AMPLIFIERS; OXIDE SEMICONDUCTORS;

ANALOG TO DIGITAL CONVERTERS; ANALOG TO DIGITALCONVERSION (A/D); COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TECHNOLOGIES; DATA CONVERSION; MIXED SIGNAL; PERFORMANCE BOTTLENECKS; TRADITIONAL ARCHITECTURE; ZERO-CROSSING DETECTORS;

ANALOG TO DIGITAL CONVERSION;

EID: 51949098123     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2007.911069     Document Type: Article

References (14)

1. P. Vorenkamp and R. Roovers, "A 12 b 50 MSample/s cascaded folding and interpolating ADC," in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 1997, pp.134-135.
2. A. G. W. Venes and R. J. van de Plassche, "An 80-MHz, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing," IEEE J. Solid-State Circuits, vol. 31, pp. 1846-1853, Dec. 1996.
3. 2," IEEE J. Solid-State Circuits, vol. 32, pp. 1887-1895, Dec. 1997.
4. S. Gupta, M. Choi, M. Inerfield, and J. Wang, "A 1 Gs/s 11 b time-interleaved ADC," in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2006, pp. 576-577.
5. R. Eschauzier, L. Kerklaan, and J. Huijsing, "A 100-MHz 100 dB operational amplifier with multipath nested miller compensation structure," IEEE J. Solid-State Circuits, vol. 27, pp. 1709-1717, Dec. 1992.
6. B. Murmann and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE J. Solid-State Circuits, vol. 38, pp. 2040-2050, Dec. 2003.
7. T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H.-S. Lee, "Comparator-based switched-capacitor circuits for scaled CMOS technologies," in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2006, pp. 220-221.
8. T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H.-S. Lee, "Comparator-based switched-capacitor circuits for scaled CMOS technologies," IEEE J. Solid-State Circuits, vol. 41, pp. 2658-2668, Dec. 2006.
9. L. Brooks and H.-S. Lee, "A zero-crossing based 8 b 200 MS/s pipelined ADC," in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2007, pp. 460-461.
10. R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Sel. Areas Commun., vol. 17, pp. 539-550, Apr. 1999.
11. R. Castello and P. R. Gray, "Performance limitations in switched-capacitor circuits," IEEE Trans. Circuits Syst., vol. CAS-32, pp. 865-876, Sep. 1985.
12. B. Murmann, "Limits on ADC power dissipation," in Analog Circuit Design, M. Steyaert, A. H. M. Roermund, and J. H. van Huijsing, Eds. Berlin, Germany: Springer, 2006.
13. J. Fiorenza, "A comparator-based switched-capacitor pipelined analog-to-digital converter," Ph.D. dissertation, Massachusetts Inst. of Technology, Mar. 15, 2007.
14. E. Iroaga and B. Murmann, "A 12 b, 75 MS/s pipelined ADC using incomplete settling," in Dig. Tech. Papers Symp. VLSI Circuits, Jun. 15-17, 2006, pp. 222-223.