A semidigital dual delay-locked loop

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 11, 1997, Pages 1683-1692

  Sidiropoulos, Stefanos ^a,b,c   Horowitz, Mark A ^a,b,c  

^a STANFORD UNIVERSITY   (United States)

^b RAMBUS INC   (United States)

^c IEEE   (United States)

Author keywords

Clock synchronization; Delay locked loops; Phase interpolation; Phase locked loops

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; PHASE LOCKED LOOPS; PHASE SHIFT; SYNCHRONIZATION; TIMING CIRCUITS;

DELAY LOCKED LOOPS; JITTER SUPPLY SENSITIVITY; PHASE INTERPOLATION; QUIESCENT SUPPLY;

DELAY CIRCUITS;

EID: 0031276490     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.641688     Document Type: Article

References (7)

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