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Volumn 57, Issue 3, 2010, Pages 153-157

A brief introduction to time-to-digital and digital-to-time converters

Author keywords

Data converters; Digital; Digital to time converters (DTCs); Reconfigurable circuits; Time mode signal processing (TMSP); Time to digital converters (TDCs)

Indexed keywords

DELAY CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FREQUENCY CONVERTERS; LOGIC SYNTHESIS; RECONFIGURABLE HARDWARE; SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 77950199322     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2010.2043382     Document Type: Article
Times cited : (161)

References (10)
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    • (2009) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.56 , Issue.9 , pp. 1908-1920
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  • 3
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  • 5
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    • Low-jitter process-independent DLL and PLL based on self-biased techniques
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    • J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol.31, no.11, pp. 1723-1732, Nov. 1996.
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    • Maneatis, J.G.1
  • 6
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    • (1995) Proc. IEEE Int. Symp. Circuits Syst. , vol.1 , pp. 637-640
    • Veillette, B.R.1    Roberts, G.W.2
  • 8
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    • Feb.
    • P. Dudek, S. Szczepanski, and J. V. Hatfield, "A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line," IEEE J. Solid-State Circuits, vol.35, no.2, pp. 240-247, Feb. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.2 , pp. 240-247
    • Dudek, P.1    Szczepanski, S.2    Hatfield, J.V.3
  • 9
    • 1342308084 scopus 로고    scopus 로고
    • A jitter characterization system using a component-invariant Vernier delay line
    • Jan.
    • A. H. Chan and G. W. Roberts, "A jitter characterization system using a component-invariant Vernier delay line," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol.12, no.1, pp. 79-95, Jan. 2004.
    • (2004) IEEE Trans. Very Large Scale Integr.(VLSI) Syst. , vol.12 , Issue.1 , pp. 79-95
    • Chan, A.H.1    Roberts, G.W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.