A self-background calibrated 6b 2.7GS/s ADC with cascade-calibrated folding-interpolating architecture

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 266-267

  Nakajima, Yuji ^a   Sakaguchi, Akemi ^a   Ohkido, Toshio ^b   Matsumoto, Tetsuya ^a   Yotsuyanagi, Michio ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b NEC Microsystems   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; FIGURE OF MERIT; ON CHIPS; POWER CONSUMPTION; PROCESS VARIATION; SAMPLING RATES;

CALIBRATION; MULTICARRIER MODULATION;

VLSI CIRCUITS;

EID: 70449379049     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. R. Taft, et al., ISSCC Dig. Tech. Papers, pp. 252-253, Feb. 2004.
2. G. Van der Plas, S. Decoutere, S. Donnay, ISSCC Dig. Tech. Papers, pp. 566-567, Feb. 2006.
3. R. Shergill, Application Note 1727, National Semiconductor
4. K. Deguchi et al., Dig. Symp. VLSI circuits, pp 64-65, June 2007.
5. A.G.W. Venes, R. J. van de Plassche, ISSCC Dig. Tech. Papers, pp. 318-319, Feb. 1996.