A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with time-domain comparator

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 246-248

  Agnes, Andrea ^a   Bonizzoni, Edoardo ^a   Malcovati, Piero ^a   Maloberti, Franco ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATORS (OPTICAL); HARMONIC DISTORTION;

COUPLING CAPACITANCE; SAR ADC; SECOND HARMONIC DISTORTION; SINGLE-ENDED; THIRD HARMONIC DISTORTIONS; TIME DOMAIN;

COMPARATOR CIRCUITS;

EID: 49549113634     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523149     Document Type: Conference Paper

References (3)

1. M. D. Scott, B. E. Boser, and K. S. J. Pister, "An Ultralow-Energy ADC for Smart Dust," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1123-1129, Jul. 2003.
2. N. Verma and A. C. Chandrakasan, "A 25mW 100kS/s 12b ADC for Wireless Micro-Sensor Applications," ISSCC Dig. Tech. Papers, pp. 222-223, Feb. 2006.
3. P. Confalonieri, M. Zamprogno, F. Girardi, et al., "A 2.7mW 1MSps 10b Analog-to-Digital Converter with Built-in Reference Buffer and 1LSB Accuracy Programmable Input Ranges," Proc. ESSCIRC, pp. 255-258, Sept. 2004.