-
1
-
-
0035273821
-
A 100-MSPS 8-b CMOS subranging ADC with parametric operation from 3.8 V down to 2.2 V
-
Mar.
-
R. C. Taft and M. R. Tursi, "A 100-MSPS 8-b CMOS subranging ADC with parametric operation from 3.8 V down to 2.2 V," IEEE J. Solid-State Circuits, vol. 36, pp. 331-338, Mar. 2001.
-
(2001)
IEEE J. Solid-state Circuits
, vol.36
, pp. 331-338
-
-
Taft, R.C.1
Tursi, M.R.2
-
3
-
-
0003135251
-
A technique for reducing differential nonlinearity errors in flash A/D converters
-
Feb.
-
K. Kattmann and J. Barrow, "A technique for reducing differential nonlinearity errors in flash A/D converters," in IEEE ISSCC Dig. Tech. Papers, Feb. 1991, pp. 170-171.
-
(1991)
IEEE ISSCC Dig. Tech. Papers
, pp. 170-171
-
-
Kattmann, K.1
Barrow, J.2
-
5
-
-
0031651831
-
A singled-ended 12 b 20 MSample/s self-calibrating pipeline A/D converter
-
Feb
-
I. Opris, L. Lewicki, and B. Wong, "A singled-ended 12 b 20 MSample/s self-calibrating pipeline A/D converter," in IEEE ISSCC Dig. Tech. Papers, Feb. 1998, pp. 138-139.
-
(1998)
IEEE ISSCC Dig. Tech. Papers
, pp. 138-139
-
-
Opris, I.1
Lewicki, L.2
Wong, B.3
-
6
-
-
0034428194
-
An 8 b 80 MSample/s pipelined ADC with background calibration
-
Feb.
-
J. Ming and S. H. Lewis, "An 8 b 80 MSample/s pipelined ADC with background calibration," in IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp. 42-43.
-
(2000)
IEEE ISSCC Dig. Tech. Papers
, pp. 42-43
-
-
Ming, J.1
Lewis, S.H.2
-
7
-
-
0031655847
-
Digital background calibration of a 10 b 40 Msample/s parallel pipelined ADC
-
Feb.
-
D. Fu, K. Dyer, S. Lewis, and P. Hurst, "Digital background calibration of a 10 b 40 Msample/s parallel pipelined ADC," in IEEE ISSCC Dig. Tech. Papers, Feb. 1998, pp. 140-141.
-
(1998)
IEEE ISSCC Dig. Tech. Papers
, pp. 140-141
-
-
Fu, D.1
Dyer, K.2
Lewis, S.3
Hurst, P.4
-
8
-
-
0031706867
-
Analog background calibration of a 10 b 40 Msample/s parallel pipelined ADC
-
Feb.
-
K. Dyer, D. Fu, S. Lewis, and P. Hurst, "Analog background calibration of a 10 b 40 Msample/s parallel pipelined ADC," in IEEE ISSCC Dig. Tech. Papers, Feb. 1998, pp. 142-143.
-
(1998)
IEEE ISSCC Dig. Tech. Papers
, pp. 142-143
-
-
Dyer, K.1
Fu, D.2
Lewis, S.3
Hurst, P.4
-
9
-
-
72849121501
-
A 12 b digital-background-calibrated algorithmic ADC with -90 dB THD
-
Feb.
-
O. E. Erdogan, P. J. Hurse, and S. H. Lewis, "A 12 b digital-background-calibrated algorithmic ADC with -90 dB THD," in IEEE ISSCC Dig. Tech. Papers, Feb. 1999, pp. 316-317.
-
(1999)
IEEE ISSCC Dig. Tech. Papers
, pp. 316-317
-
-
Erdogan, O.E.1
Hurse, P.J.2
Lewis, S.H.3
-
10
-
-
0033281382
-
GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link
-
June
-
W. Ellersick, C.-K. K. Yang, M. Horowitz, and W. Dally, "GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 1999, pp. 49-52.
-
(1999)
IEEE Symp. VLSI Circuits Dig. Tech. Papers
, pp. 49-52
-
-
Ellersick, W.1
Yang, C.-K.K.2
Horowitz, M.3
Dally, W.4
-
11
-
-
0034476097
-
A dual-mode 700-MSamples/s 6-bit 200-MSamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process
-
Dec.
-
K. Nagaraj, D. A. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, and T. R. Viswanathan, "A dual-mode 700-MSamples/s 6-bit 200-MSamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process," IEEE J. Solid-State Circuits, vol. 35, pp. 1760-1768, Dec. 2000.
-
(2000)
IEEE J. Solid-state Circuits
, vol.35
, pp. 1760-1768
-
-
Nagaraj, K.1
Martin, D.A.2
Wolfe, M.3
Chattopadhyay, R.4
Pavan, S.5
Cancio, J.6
Viswanathan, T.R.7
-
12
-
-
0034430276
-
A 6 b 800 Msamples/s CMOS A/D convener
-
Feb.
-
K. Sushihara, H. Kimura, Y. Okamoto, K. Nishimura, and A. Matsuzawa, "A 6 b 800 Msamples/s CMOS A/D convener," in IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp. 428-429.
-
(2000)
IEEE ISSCC Dig. Tech. Papers
, pp. 428-429
-
-
Sushihara, K.1
Kimura, H.2
Okamoto, Y.3
Nishimura, K.4
Matsuzawa, A.5
-
13
-
-
0035058178
-
A 6 b 1.1 Gsample/s CMOS A/D converter
-
Feb.
-
G. Geelen. "A 6 b 1.1 Gsample/s CMOS A/D converter," in IEEE ISSCC Dig. Tech. Papers, Feb. 2001, pp. 128-129.
-
(2001)
IEEE ISSCC Dig. Tech. Papers
, pp. 128-129
-
-
Geelen, G.1
-
14
-
-
0035046949
-
A 6 b 1.3 GSample/s A/D converter in 0.35 m CMOS
-
Feb.
-
M. Choi and A. A. Abidi, "A 6 b 1.3 GSample/s A/D converter in 0.35 m CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2001, pp. 126-127.
-
(2001)
IEEE ISSCC Dig. Tech. Papers
, pp. 126-127
-
-
Choi, M.1
Abidi, A.A.2
-
15
-
-
0036113497
-
A 6 bit 1.6 GS/s flash ADC in 0.18 μm CMOS using averaging termination
-
Feb.
-
P. Scholtens and M. Vertregt, "A 6 bit 1.6 GS/s flash ADC in 0.18 μm CMOS using averaging termination," in IEEE ISSCC Dig. Tech. Papers, Feb. 2002. pp. 168-169.
-
(2002)
IEEE ISSCC Dig. Tech. Papers
, pp. 168-169
-
-
Scholtens, P.1
Vertregt, M.2
-
16
-
-
0036108540
-
A 4 Gsample/s 8 b ADC in 0.35 μm CMOS
-
Feb.
-
K. Poulton, R. Neff, A. Muto, W. Liu, A. Burstein, and M. Heshami, "A 4 Gsample/s 8 b ADC in 0.35 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2002, pp. 166-167.
-
(2002)
IEEE ISSCC Dig. Tech. Papers
, pp. 166-167
-
-
Poulton, K.1
Neff, R.2
Muto, A.3
Liu, W.4
Burstein, A.5
Heshami, M.6
-
17
-
-
0038645290
-
A 2 GS/s 6 b ADC in 0.18 μm CMOS
-
Feb.
-
X. Jiang, Z. Wang, and M. F. Chang, "A 2 GS/s 6 b ADC in 0.18 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 322-323.
-
(2003)
IEEE ISSCC Dig. Tech. Papers
, pp. 322-323
-
-
Jiang, X.1
Wang, Z.2
Chang, M.F.3
-
18
-
-
0037630792
-
A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 μm CMOS
-
Feb.
-
K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, and A. Montijo, "A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 318-319.
-
(2003)
IEEE ISSCC Dig. Tech. Papers
, pp. 318-319
-
-
Poulton, K.1
Neff, R.2
Setterberg, B.3
Wuppermann, B.4
Kopley, T.5
Jewett, R.6
Pernillo, J.7
Tan, C.8
Montijo, A.9
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