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Volumn 52, Issue 5, 2005, Pages 246-250

A Low-Voltage 10-Bit CMOS DAC in 0.01-mm2Die Area

Author keywords

Die area; digital analog (D A); digital to analog conversion (DAC); low voltage

Indexed keywords

CALIBRATION; DIGITAL TO ANALOG CONVERSION; ELECTRIC CURRENTS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC POTENTIAL; TRANSISTORS;

EID: 20444402580     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2005.843595     Document Type: Article
Times cited : (26)

References (6)
  • 1
    • 0018724241 scopus 로고
    • An inherently linear 12 bit DAC
    • Dec.
    • J. A. Schoeff, “An inherently linear 12 bit DAC,” IEEE J. Solid-State Circuits, vol. SC-14, no. 12, pp. 904–911, Dec. 1979.
    • (1979) IEEE J. Solid-State Circuits , vol.SC-14 , Issue.12 , pp. 904-911
    • Schoeff, J.A.1
  • 4
    • 0022891057 scopus 로고
    • Characterization and modeling of mismatch in MOS transistors for precision analog design
    • Dec.
    • K. Lakshmikumar, R. Hadaway, and M. Copeland, “Characterization and modeling of mismatch in MOS transistors for precision analog design,” IEEE J. Solid-State Circuits, vol. SC-21, no. 12, pp. 1057–1066, Dec. 1986.
    • (1986) IEEE J. Solid-State Circuits , vol.SC-21 , Issue.12 , pp. 1057-1066
    • Lakshmikumar, K.1    Hadaway, R.2    Copeland, M.3
  • 6
    • 0016620207 scopus 로고
    • All-MOS charge redistribution analog-to-digital conversion techniques
    • Dec.
    • J. McCreary and P. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques,” IEEE J. Solid-State Circuits, vol. SC-10, no. 12, pp. 371–385, Dec. 1975.
    • (1975) IEEE J. Solid-State Circuits , vol.SC-10 , Issue.12 , pp. 371-385
    • McCreary, J.1    Gray, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.