-
1
-
-
0346237371
-
"A 12 b 75 MS/s pipelined ADC using open-loop residue amplification"
-
Feb
-
B. Murmann and B. E. Boser, "A 12 b 75 MS/s pipelined ADC using open-loop residue amplification," in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2003, pp. 328-329.
-
(2003)
Int. Solid-State Circuits Conf. Tech. Dig.
, pp. 328-329
-
-
Murmann, B.1
Boser, B.E.2
-
2
-
-
0023599417
-
"A pipelined 5-Msample/s 9-bit analog-to-digital converter"
-
Dec
-
S. H. Lewis and P. R. Gray, "A pipelined 5-Msample/s 9-bit analog-to-digital converter," IEEE J. Solid-State Circuits, vol. SSC-22, no. 6, pp. 954-961, Dec. 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.SSC-22
, Issue.6
, pp. 954-961
-
-
Lewis, S.H.1
Gray, P.R.2
-
3
-
-
0033893576
-
"Digital cancellation of D/A converter noise in pipelined A/D converters"
-
Mar
-
I. Galton, "Digital cancellation of D/A converter noise in pipelined A/ D converters," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 3, pp. 185-196, Mar. 2000.
-
(2000)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.47
, Issue.3
, pp. 185-196
-
-
Galton, I.1
-
4
-
-
0026141224
-
"A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS"
-
Apr
-
Y.-M. Lin, B. Kim, and P. Gray, "A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS," IEEE J. Solid-State Circuits vol. 26, no. 4, pp. 628-636, Apr. 1991.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, Issue.4
, pp. 628-636
-
-
Lin, Y.-M.1
Kim, B.2
Gray, P.3
-
5
-
-
0026999467
-
"Digital-domain calibration of multistep analog-to-digital converters"
-
Dec
-
S.-H. Lee and B.-S. Song, "Digital-domain calibration of multistep analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1679-1688, Dec. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, Issue.12
, pp. 1679-1688
-
-
Lee, S.-H.1
Song, B.-S.2
-
6
-
-
0027853599
-
"A 15-b 1-Msample/s digitally self-calibrated pipeline ADC"
-
Dec
-
A. N. Karanicolas, H.-S. Lee, and K. L. Barcrania, "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207-1215, Dec. 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, Issue.12
, pp. 1207-1215
-
-
Karanicolas, A.N.1
Lee, H.-S.2
Barcrania, K.L.3
-
7
-
-
18544399632
-
"A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD"
-
Dec
-
O. E. Erdog̊an, P. J. Hurst, and S. H. Lewis, "A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1812-1820, Dec. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.12
, pp. 1812-1820
-
-
Erdog̊an, O.E.1
Hurst, P.J.2
Lewis, S.H.3
-
8
-
-
0031359733
-
"A 15-b, 5-Msample/s low-spurious CMOS ADC"
-
Dec
-
S.-U. Kwak, B.-S. Song, and K. Bacrania, "A 15-b, 5-Msample/s low-spurious CMOS ADC," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1866-1875, Dec. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, Issue.12
, pp. 1866-1875
-
-
Kwak, S.-U.1
Song, B.-S.2
Bacrania, K.3
-
9
-
-
84893733806
-
"An 8-bit 13-MSamples/s digital-background-calibrated algorithmic ADC"
-
Sep
-
E. B. Blecker, O. E. Erdog̊an, P. J. Hurst, and S. H. Lewis, "An 8-bit 13-MSamples/s digital-background-calibrated algorithmic ADC," in Proc. Eur. Solid-State Circuits Conf., Sep. 2000, pp. 372-375.
-
(2000)
Proc. Eur. Solid-State Circuits Conf.
, pp. 372-375
-
-
Blecker, E.B.1
Erdog̊an, O.E.2
Hurst, P.J.3
Lewis, S.H.4
-
10
-
-
0034428194
-
"An 8 b 80 Msample/s pipelined ADC with background calibration"
-
Feb
-
J. Ming and S. H. Lewis, "An 8 b 80 Msample/s pipelined ADC with background calibration," in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2000, pp. 42-43.
-
(2000)
Int. Solid-State Circuits Conf. Tech. Dig.
, pp. 42-43
-
-
Ming, J.1
Lewis, S.H.2
-
11
-
-
0026836960
-
"A 10-b 20-Msample/s analog-to-digital converter"
-
Mar
-
S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, "A 10-b 20-Msample/s analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351-358, Mar. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, Issue.3
, pp. 351-358
-
-
Lewis, S.H.1
Fetterman, H.S.2
Gross Jr., G.F.3
Ramachandran, R.4
Viswanathan, T.R.5
-
12
-
-
0033893202
-
"Gain error correction technique for pipelined analogue-to-digital converters"
-
Mar
-
E. J. Siragusa and I. Galton, "Gain error correction technique for pipelined analogue-to-digital converters," Electron. Lett., vol. 36, no. 7, pp. 617-618, Mar. 2000.
-
(2000)
Electron. Lett.
, vol.36
, Issue.7
, pp. 617-618
-
-
Siragusa, E.J.1
Galton, I.2
-
13
-
-
0141954044
-
"Backgound calibration techniques for multistage pipelined ADC's with digital redundancy"
-
Sep
-
J. Li and U.-K. Moon, "Backgound calibration techniques for multistage pipelined ADC's with digital redundancy," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 9, pp. 531-538, Sep. 2003.
-
(2003)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.
, vol.50
, Issue.9
, pp. 531-538
-
-
Li, J.1
Moon, U.-K.2
-
14
-
-
12944292363
-
"High-resolution pipelined analog-to-digital conversion"
-
Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Univ. California at Berkeley, Berkeley, CA
-
S. Sutarja, "High-resolution pipelined analog-to-digital conversion," Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Univ. California at Berkeley, Berkeley, CA, 1988.
-
(1988)
-
-
Sutarja, S.1
-
15
-
-
0035060903
-
"A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist"
-
Feb
-
D. Kelly, W. Yang, I. Mehr, M. Sayuk, and L. Singer, "A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist," in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2001, pp. 134-135.
-
(2001)
Int. Solid-State Circuits Conf. Tech. Dig.
, pp. 134-135
-
-
Kelly, D.1
Yang, W.2
Mehr, I.3
Sayuk, M.4
Singer, L.5
-
17
-
-
0024175268
-
"A CMOS operational amplifier with load- and signal-independent settling time"
-
Aug
-
R. Klinke, B. J. Hosticka, H.-J. Pfleiderer, and G. Zimmer, "A CMOS operational amplifier with load- and signal-independent settling time," in Symp. VLSI Circuits Tech. Dig., Aug. 1988, pp. 7-8.
-
(1988)
Symp. VLSI Circuits Tech. Dig.
, pp. 7-8
-
-
Klinke, R.1
Hosticka, B.J.2
Pfleiderer, H.-J.3
Zimmer, G.4
-
18
-
-
2442637789
-
"A 12 b 80 MS/s pipelined ADC with bootstrapped digital calibration"
-
Feb
-
C. R. Grace, P. J. Hurst, and S. H. Lewis, "A 12 b 80 MS/s pipelined ADC with bootstrapped digital calibration," in Int. Solid-State Circuits Conf. Tech. Dig., vol. 47, Feb. 2004, pp. 460-461.
-
(2004)
Int. Solid-State Circuits Conf. Tech. Dig.
, vol.47
, pp. 460-461
-
-
Grace, C.R.1
Hurst, P.J.2
Lewis, S.H.3
-
19
-
-
0036912842
-
"A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration"
-
Dec
-
S. M. Jamal, D. Fu, N. C. J. Chang, P. J. Hurst, and S. H. Lewis, "A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1618-1627, Dec. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.12
, pp. 1618-1627
-
-
Jamal, S.M.1
Fu, D.2
Chang, N.C.J.3
Hurst, P.J.4
Lewis, S.H.5
-
20
-
-
0035693616
-
2 with mixed-signal chopping and calibration"
-
Dec
-
2 with mixed-signal chopping and calibration," IEEE J. Solid-State Circuits vol. 36, no. 12, pp. 1859-1867, Dec. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.12
, pp. 1859-1867
-
-
Ploeg, H.1
Hoogzaad, G.2
Termeer, H.A.H.3
Vertregt, M.4
Roovers, R.L.J.5
-
21
-
-
0032597894
-
"CMOS pipelined ADC employing dither to improve linearity"
-
May
-
H. S. Fetterman, D. G. Martin, and D. A. Rich, "CMOS pipelined ADC employing dither to improve linearity," in Proc. IEEE Custom Integrated Circuits Conf., May 1999, pp. 109-112.
-
(1999)
Proc. IEEE Custom Integrated Circuits Conf.
, pp. 109-112
-
-
Fetterman, H.S.1
Martin, D.G.2
Rich, D.A.3
|