A 78 dB SNDR 87 mW 20 MHz bandwidth continuous-time δσ ADC with VCO-based integrator and quantizer implemented in 0.13 μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 12, 2009, Pages 3344-3358

  Park, Matthew ^a,b   Perrott, Michael H ^c  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b MCKINSEY AND COMPANY   (United States)

^c SiTime Corporation   (United States)

Author keywords

; Analog to digital conversion; Quantizer; Ring oscillator; VCO based; Voltage controlled oscillator (VCO)

Indexed keywords

ACTIVE AREA; ANALOG TO DIGITAL CONVERTERS; CONTINUOUS TIME; FOURTH-ORDER; NOISE-SHAPING; OUTPUT FREQUENCY; OUTPUT PHASE; QUANTIZERS; VOLTAGE CONTROLLED OSCILLATOR;

ANALOG TO DIGITAL CONVERSION; CONTINUOUS TIME SYSTEMS; ELECTRIC CONVERTERS; MULTICARRIER MODULATION; TIME VARYING SYSTEMS;

VARIABLE FREQUENCY OSCILLATORS;

EID: 72949117926     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2032703     Document Type: Conference Paper

References (38)

1. M. Park and M. Perrott, "A 0.13 μm CMOS 78 dB SNDR 87 mW 20 MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer," presented at the IEEE Int. Solid- State Circuits Conf., San Francisco, CA, 2009, paper 9.5.
2. M. Park, "A fourth-order continuous-time ΔΣ ADC with VCO-based integrator and quantizer," Ph.D. dissertation, Massachusetts Inst. Technol., Cambridge, MA, Feb. 2009.
3. M. Hovin, A. Olsen, T. Sverre, and C. Toumazou, " ΔΣ modulators using frequency-modulated intermediate values," IEEE. J. Solid-State Circuits, vol.32, no.1, pp. 13-22, Jan. 1997.
4. A. Iwata, N. Sakimura, M. Nagata, and T. Morie, "The architecture of ΔΣ analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer," IEEE Trans. Circuits Syst. II, vol.46, no.7, pp. 941-945, Jul. 1999.
5. R. Naiknaware, H. Tang, and T. S. Fiez, "Time- referenced single-path multi-bit ADC using a VCO-based quantizer," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.47, no.7, pp. 596-602, Jul. 2000.
6. J. Kim and S. Cho, "A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator," in Proc. 2006 IEEE Int. Symp. Circuits and Systems (ISCAS), May 2006, pp. 3934-3937.
7. M. Straayer and M. Perrott, "A 12-bit 10-MHz bandwidth, continuoustime sigma-delta ADC with a 5-bit, 950-MS/S VCO-based quantizer," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 805-814, Apr. 2008.
8. V. B. Boros, "A digital proportional integral and derivative feedback controller for power conditioning equipment," in IEEE Power Electronics Specialists Conf. Rec., Jun. 1977, pp. 135-141.
9. J. P. Hurrell, D. C. Pridmore-Brown, and A. H. Silver, "Analog-to-digital conversion with unlatched SQUID's," IEEE Trans. Electron Devices, vol.ED-27, no.10, pp. 1887-1896, Oct. 1980.
10. M. Miller, "Multi-bit continuous-time sigma-delta ADC," U.S. Patent 6,700,520, Mar. 2, 2004.
11. R. Schreier, ΔΣ Toolbox. [Online]. Available: http://www.mathworks.com/matlabcentral/fileexchange/loadFile.do?objectId= 19&objectType=file
12. G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, "A 20 mW 640-MHz CMOS continuous-time sigma-delta ADC with 20-MHz signal bandwidth, 80-dB dynamic range, and 12-bit ENOB," IEEE J. Solid-State Circuits, vol.41, no.12, pp. 2641- 2649, Dec. 2006.
13. S. Yan and E. Sanchez-Sinencio, "A continuous-time modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth," IEEE J. Solid- State Circuits, vol.39, no.1, pp. 75-86, Jan. 2004.
14. S. Paton, A. Di Giandomenico, L. Hernandez, A. Wiesbauer, T. Potcher, and M. Clara, "A 70-mW 300-MHz CMOS continuous-time ΔΣ ADC with 15-MHz bandwidth and 11 bits of resolution," IEEE J. Solid-State Circuits, vol.39, no.7, pp. 1056-1063, Jul. 2004.
15. L. Breems, R. Rutten, and G. Wetzker, "A cascaded continuous-time ΔΣ modulator with 67-dB dynamic range in 10 MHz bandwidth," IEEE J. Solid-State Circuits, vol.39, no.12, pp. 2152-2160, Dec. 2004.
16. E. Alon, V. Stojanovic, and M. A. Horowitz, "Circuits and techniques for high-resolution measurement of on-chip power supply noise," IEEE J. Solid-State Circuits, vol.40, no.4, pp. 820-828, Apr. 2005.
17. M. H. Perrott, "Fast and accurate behavioral simulation of fractional-N synthesizers and other PLL/DLL circuits," in Proc. Design Automation Conf. (DAC), Jun. 2002, pp. 498-503.
18. B. Nikolic, V. G. Oklobzija, V. Stojanovic, W. Jia, J. K.-S. Chiu, and M. M.-T. Leung, "Improved sense amplifier-based flip-flop: Design and measurements," IEEE J. Solid-State Circuits, vol.35, no.6, pp. 876-884, Jun. 2000.
19. N. Yaghini and D. Johns, "A 43 mW CT complex ΔΣ ADC with 23 MHz of signal bandwidth and 68.8 dB SNDR," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 502-503.
20. R. Schoofs, M. Steyaert, and W. Sansen, "A design- optimized continuous- time ΔΣ ADC for WLAN applications," IEEE Trans. Circuits Syst. I, Reg. Papers, vol.54, no.1, pp. 209-217, Jan. 2007.
21. R. Schoofs, M. Steyaert, and W. Sansen, "A 1 GHz continuous-time sigma-delta A/D converter in 90 nm standard CMOS," in IEEE MTT-S Tech. Dig., 2005, pp. 1287-1290.
22. R. Adams, K. Q. Nguyen, and K. Sweetland, "A 113- dB SNR oversampling DAC with segmented noise-shaped scrambling," IEEE J. Solid- State Circuits, vol.33, no.12, pp. 1871-1878, Dec. 1998.
23. X. Fan, C. Mishra, and E. Sanchez-Sinencio, "Single Miller capacitor frequency compensation technique for low-power multistage amplifiers," IEEE J. Solid-State Circuits, vol.40, no.3, pp. 584-592, Mar. 2005.
24. S. Norsworthy, R. Schreier, and G. Temes, Delta- Sigma Data Converters. New York: Wiley Blackwell, 1996.
25. I. Kipnis, S. Chiu, M. Loyer, J. Carrigan, J. Rapp, P. Johansson, D. Westberg, and J. Johansson, "A 900MHz UHF RFID reader transceiver IC," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 214, 598.
26. F. Esfahani, P. Basedau, R. Ryter, and R. Becker, "A fourth-order continuous-time complex sigma-delta ADC for low-IF GSM and EDGE receivers," in Symp. VLSI Circuits Dig., 2003, pp. 75-78.
27. L. Breems, R. Rutten, R. Veldhoven, G.Weide, and H. Termeer, "A 56 mW CT quadrature cascaded ΔΣ modulator with 77 dB DR in a near zero-IF 20 MHz band," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 238, 599.
28. R. Veldhoven, R. Rutten, and L. Breems, "An inverter-based hybrid ΔΣ modulator," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 492, 630.
29. Y. Shu, B. Song, and K. Bacrania, "A 65 nm CMOS CT ΔΣ modulator with 81 dB DR and 8MHzBW auto-tuned by pulse injection," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 500, 631.
30. S. Ouzounov, R. Veldhoven, C. Bastiaansen, K. vongehr, R. Wegberg, G. Geelen, L. Breems, and A. Roermund, "A 1.2 V 121-mode CT ΔΣ modulator for wireless receivers in 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 242-600.
31. W. Yang, W. Schofield, H. Shibata, S. Korrapati, A. Shaikh, N. Abaskharoun, and D. Ribner, "A 100 mW 10 MHz-BW CT ΔΣ modulator with 87 dB DR and 91 dBc IMD," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 498, 631.
32. U. Wismar, D. Wisland, and P. Andreani, "A 0.2 V 0.44 μW, 20 kHz ΔΣ analog to digital modulator with 57 fJ/conversion FoM," in Proc. European Solid State Circuits Conf. (ESSCIRC), 2006, pp. 187-190.
33. U. Wismar, D. Wisland, and P. Andreani, "A 0.2 V 7.5 μW, 20 kHz ΔΣ modulator with 69 dB SNR in 90 nm CMOS," in Proc. European Solid State Circuits Conf. (ESSCIRC), 2007, pp. 206-209.
34. M. Park, "Behavioral simulation of a 4th-order CT delta-sigma ADC with VCO-based integrator and quantizer," [Online]. Available: http://www.cppsim.com/tutorials.html
35. S.-J. Huang and Y.-Y. Lin, "A 1.2 V 2 MHz BW 0.084 mm CT ΔΣ ADC with - 97.7 dBc THD and 80 dB DR using low-latency DEM," in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 172-173, 173a.
36. T. Riley, N. M. Filiol, D. Qinghong, and J. Kostamovaara, "Techniques for inband noise reduction in ΔΣ synthesizers," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.50, no.11, pp. 794-803, Nov. 2003.
37. R. Baird and T. Fiez, "Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.42, no.7, pp. 753-762, Jul. 1995.
38. J. Rabaey, Digital Integrated Circuits: A Design Perspective. Englewood Cliffs, NJ: Prentice-Hall, 1996.