-
1
-
-
0032316466
-
A 12-bit intrinsic accuracy high-speed CMOS DAC
-
Dec
-
J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 12-bit intrinsic accuracy high-speed CMOS DAC," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, Issue.12
, pp. 1959-1969
-
-
Bastos, J.1
Marques, A.M.2
Steyaert, M.S.J.3
Sansen, W.4
-
2
-
-
0033280679
-
2 random walk CMOS DAC
-
Dec
-
2 random walk CMOS DAC," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1708-1717, Dec. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.12
, pp. 1708-1717
-
-
Van Der Plas, G.A.M.1
Vandenbussche, J.2
Sansen, W.3
Steyaert, M.S.J.4
Gielen, G.G.E.5
-
3
-
-
0348233277
-
A 1.5-V 1.4-bit 100-MS/s self-calibrated DAC
-
Dec
-
Y. Cong and R. L. Geiger, "A 1.5-V 1.4-bit 100-MS/s self-calibrated DAC," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2051-2060, Dec. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.12
, pp. 2051-2060
-
-
Cong, Y.1
Geiger, R.L.2
-
4
-
-
0034479476
-
A self-trimming 14-b 100-MS/s CMOS DAC
-
Dec
-
A. R. Bugeja and B. S. Song, "A self-trimming 14-b 100-MS/s CMOS DAC," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1841-1852, Dec. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.12
, pp. 1841-1852
-
-
Bugeja, A.R.1
Song, B.S.2
-
5
-
-
0038645513
-
A 16 b 400 MS/s DAC with < -80 dBc IMD to 300 MHz and < -160 dBm/Hz noise power spectral density
-
W. Schofield, D. Mercer, and L. St. Onge, "A 16 b 400 MS/s DAC with < -80 dBc IMD to 300 MHz and < -160 dBm/Hz noise power spectral density," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 126-127.
-
(2003)
IEEE ISSCC Dig. Tech. Papers
, pp. 126-127
-
-
Schofield, W.1
Mercer, D.2
St. Onge, L.3
-
6
-
-
2442689342
-
A 200 MS/s 14b 97 m W DAC in 0.18 μm CMOS
-
Q. Huang, P. A. Francese, C. Martelli, and J. Nielsen, "A 200 MS/s 14b 97 m W DAC in 0.18 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 364-365.
-
(2004)
IEEE ISSCC Dig. Tech. Papers
, pp. 364-365
-
-
Huang, Q.1
Francese, P.A.2
Martelli, C.3
Nielsen, J.4
-
7
-
-
0038529372
-
A 300-MS/s 1.4-bit digital-to-analog converter in logic CMOS
-
May
-
J. Hyde, T. Humes, C. Diorio, M. Thomas, and M. Figueroa, "A 300-MS/s 1.4-bit digital-to-analog converter in logic CMOS," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 734-740, May 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.5
, pp. 734-740
-
-
Hyde, J.1
Humes, T.2
Diorio, C.3
Thomas, M.4
Figueroa, M.5
-
8
-
-
28144440308
-
A 1.2 Gs/s 15b DAC for precision signal generation
-
B. Jewett, J. Liu, and K. Poulton, "A 1.2 Gs/s 15b DAC for precision signal generation," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 110-111.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
, pp. 110-111
-
-
Jewett, B.1
Liu, J.2
Poulton, K.3
-
9
-
-
3042819299
-
2
-
Jul
-
2," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1064-1072, Jul. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.7
, pp. 1064-1072
-
-
Sullivan, K.O.1
Gorman, C.2
Hennessy, M.3
Callaghan, V.4
-
10
-
-
52249101587
-
-
MB86061 12-bit 400 MS/s digital to analog converter. Fujitsu
-
MB86061 12-bit 400 MS/s digital to analog converter. Fujitsu.
-
-
-
-
11
-
-
39749115074
-
A 14b 100 MS/s DAC with fully segmented dynamic element matching
-
K. L. Chan and I. Galton, "A 14b 100 MS/s DAC with fully segmented dynamic element matching," in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 582-583, 675.
-
(2006)
IEEE ISSCC Dig. Tech. Papers
-
-
Chan, K.L.1
Galton, I.2
-
12
-
-
39749120922
-
A 150 MS/s 14-bit segmented DEM DAC with greater than 83 dB of SFDR across the Nyquist band
-
Jun, 14
-
K. L. Chan, J. Zhu, and I. Galton, "A 150 MS/s 14-bit segmented DEM DAC with greater than 83 dB of SFDR across the Nyquist band," in Symp. VLSI Circuits, Jun, 14, 2007.
-
(2007)
Symp. VLSI Circuits
-
-
Chan, K.L.1
Zhu, J.2
Galton, I.3
-
13
-
-
16244385650
-
A 2-GS/s 3-bit Δ∑ -modulated DAC with tunable bandpass mismatch shaping
-
Mar
-
T. S. Kaplan, J. F. Jensen, C. H. Fields, and M.-C. F. Chang, "A 2-GS/s 3-bit Δ∑ -modulated DAC with tunable bandpass mismatch shaping," IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 603-610, Mar. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.3
, pp. 603-610
-
-
Kaplan, T.S.1
Jensen, J.F.2
Fields, C.H.3
Chang, M.-C.F.4
-
14
-
-
0009492792
-
D/A conversion: Amplitude and time error mapping optimization
-
Sep
-
K. Doris, C. Lin, D. Leenaerts, and A. van Roermund, "D/A conversion: amplitude and time error mapping optimization," in 8th IEEE Int. Conf. Electronics, Circuits and Systems, Sep. 2001, vol. 2, pp. 863-866.
-
(2001)
8th IEEE Int. Conf. Electronics, Circuits and Systems
, vol.2
, pp. 863-866
-
-
Doris, K.1
Lin, C.2
Leenaerts, D.3
van Roermund, A.4
-
15
-
-
34548862626
-
Statistical analysis of mapping technique for timing error correction, in current-steering DACs
-
May
-
Y. Tang, H. Hegt, A. van Roermund, K. Doris, and J. Briaire, "Statistical analysis of mapping technique for timing error correction, in current-steering DACs," in IEEE Int. Symp. Circuits and Systems (ISCAS'07), May 2007, pp. 1225-1228.
-
(2007)
IEEE Int. Symp. Circuits and Systems (ISCAS'07)
, pp. 1225-1228
-
-
Tang, Y.1
Hegt, H.2
van Roermund, A.3
Doris, K.4
Briaire, J.5
-
16
-
-
52249091815
-
Segmented dynamic element matching for high-resolution digital-to-analog conversion
-
under second review, submitted
-
K. L. Chan, N. Rakuljic, and I. Galton, "Segmented dynamic element matching for high-resolution digital-to-analog conversion," IEEE Trans. Circuits Syst. I: Reg. Papers, submitted, under second review.
-
IEEE Trans. Circuits Syst. I: Reg. Papers
-
-
Chan, K.L.1
Rakuljic, N.2
Galton, I.3
-
17
-
-
27844440775
-
High-performance direct digital frequency synthesizer in 0.25 μm CMOS using dual-slope approximation
-
Nov
-
D. D. Caro and A. G. M. Strollo, "High-performance direct digital frequency synthesizer in 0.25 μm CMOS using dual-slope approximation," IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2220-2227, Nov. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.11
, pp. 2220-2227
-
-
Caro, D.D.1
Strollo, A.G.M.2
-
18
-
-
0033886802
-
A 3.3 V single-poly CMOS audio ADC delta-sigma modulator with 98 dB peak SINAD and 105 dB peak SFDR
-
Mar
-
E. Fogleman, I. Galton, W. Huff, and H. T. Jensen, "A 3.3 V single-poly CMOS audio ADC delta-sigma modulator with 98 dB peak SINAD and 105 dB peak SFDR," IEEE J. Solid-State Circuits, vol.. 35, no. 3, pp. 297-307, Mar. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.3
, pp. 297-307
-
-
Fogleman, E.1
Galton, I.2
Huff, W.3
Jensen, H.T.4
-
19
-
-
28144435050
-
A 12b 500 MS/s DAC with >70 dB SFDR up to 1.20 MHz in 0.1.8 μm CMOS
-
K. Doris, J. Briaire, D. Leenaerts, M. Vertragt, and A. van Roermund, "A 12b 500 MS/s DAC with >70 dB SFDR up to 1.20 MHz in 0.1.8 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 116-117.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
, pp. 116-117
-
-
Doris, K.1
Briaire, J.2
Leenaerts, D.3
Vertragt, M.4
van Roermund, A.5
-
20
-
-
52249083762
-
-
DAC5672: Dual 14-Bit 200 MSPS DAC. Texas Instruments, Inc.
-
DAC5672: Dual 14-Bit 200 MSPS DAC. Texas Instruments, Inc.
-
-
-
-
21
-
-
52249092674
-
-
MAX5891: 16-Bit, 600 Msps high dynamic performance DAC with differential LVDS inputs. Maxim.
-
MAX5891: 16-Bit, 600 Msps high dynamic performance DAC with differential LVDS inputs. Maxim.
-
-
-
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