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Volumn 2005, Issue , 2005, Pages 375-382

Scaling of analog-to-digital converters into ultra-deep-submicron CMOS

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EFFICIENCY; TRANSISTORS; VOLTAGE CONTROL;

EID: 33847133060     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568684     Document Type: Conference Paper
Times cited : (59)

References (101)
  • 1
    • 4544381394 scopus 로고    scopus 로고
    • A 4GS/s 6b flash ADC in 0.13μm CMOS
    • C. Paulus et al., "A 4GS/s 6b flash ADC in 0.13μm CMOS," VLSI Symposium, 2004, pp. 420-423.
    • (2004) VLSI Symposium , pp. 420-423
    • Paulus, C.1
  • 2
    • 0038494530 scopus 로고    scopus 로고
    • A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS
    • July
    • K. Uyttenhove et al., "A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS," JSSC, vol. 38, pp. 1115-1122, July 2003.
    • (2003) JSSC , vol.38 , pp. 1115-1122
    • Uyttenhove, K.1
  • 4
    • 0036917305 scopus 로고    scopus 로고
    • A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination
    • Dec
    • P. C. S. Soholtens et al., "A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination," JSSC, vol. 37, pp. 1599-1609, Dec. 2002.
    • (2002) JSSC , vol.37 , pp. 1599-1609
    • Soholtens, P.C.S.1
  • 5
    • 0035696160 scopus 로고    scopus 로고
    • A 6-b 1.3-GS/s A/D converter in 0.35-μm CMOS
    • Dec
    • M. Choi et al., "A 6-b 1.3-GS/s A/D converter in 0.35-μm CMOS," JSSC, vol. 36, pp. 1847-1858, Dec. 2001.
    • (2001) JSSC , vol.36 , pp. 1847-1858
    • Choi, M.1
  • 6
    • 0034430276 scopus 로고    scopus 로고
    • A 6b 800MS/s CMOS A/D converter
    • K. Sushihara, et al., "A 6b 800MS/s CMOS A/D converter," ISSCC, 2000, pp. 428-429.
    • (2000) ISSCC , pp. 428-429
    • Sushihara, K.1
  • 7
    • 0034476097 scopus 로고    scopus 로고
    • A dual-mode 700-MS/s 6-bit 200-MS/s 7-bit A/D converter in a 0.25-μm digital CMOS process
    • Dec
    • K. Nagaraj, et al., "A dual-mode 700-MS/s 6-bit 200-MS/s 7-bit A/D converter in a 0.25-μm digital CMOS process," JSSC, vol. 35, pp. 1760-1768, Dec. 2000.
    • (2000) JSSC , vol.35 , pp. 1760-1768
    • Nagaraj, K.1
  • 8
    • 0032316106 scopus 로고    scopus 로고
    • A CMOS 6-b, 400-MS/s ADC with error correction
    • Dec
    • S. Tsukamoto, et al., "A CMOS 6-b, 400-MS/s ADC with error correction," JSSC, vol. 33, pp. 1939-1947, Dec. 1998.
    • (1998) JSSC , vol.33 , pp. 1939-1947
    • Tsukamoto, S.1
  • 9
    • 0003135251 scopus 로고
    • A Technique for Reducing Differential Nonlinearity Errors in Flash ADC
    • K. Kattmann et al., "A Technique for Reducing Differential Nonlinearity Errors in Flash ADC," ISSCC, 1991, pp. 170-171.
    • (1991) ISSCC , pp. 170-171
    • Kattmann, K.1
  • 10
    • 4544256284 scopus 로고    scopus 로고
    • A 600-MSPS 8-bit folding ADC in 0.18-μm CMOS
    • W. Zheng-Yu, et al., "A 600-MSPS 8-bit folding ADC in 0.18-μm CMOS," VLSI Symposium, 2004, pp. 424-427.
    • (2004) VLSI Symposium , pp. 424-427
    • Zheng-Yu, W.1
  • 11
    • 10444248089 scopus 로고    scopus 로고
    • A 1.8-V 1.6-GS/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency
    • Dec
    • R. C. Taft, et al., "A 1.8-V 1.6-GS/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency," JSSC, vol. 39, pp. 2107, Dec. 2004.
    • (2004) JSSC , vol.39 , pp. 2107
    • Taft, R.C.1
  • 12
    • 2442648846 scopus 로고    scopus 로고
    • An 8b 600MS/S 200mW CMOS folding A/D Converter using an amplifier preset technique
    • G. Geelen et al., "An 8b 600MS/S 200mW CMOS folding A/D Converter using an amplifier preset technique," ISSCC, 2004, pp. 254-255.
    • (2004) ISSCC , pp. 254-255
    • Geelen, G.1
  • 13
    • 0034482479 scopus 로고    scopus 로고
    • A 13-b 40-MS/s CMOS pipelined folding ADC w/ background offset trimming
    • Dec
    • M. Choe, et al., "A 13-b 40-MS/s CMOS pipelined folding ADC w/ background offset trimming," JSSC, vol. 35, p. 1781, Dec. 2000.
    • (2000) JSSC , vol.35 , pp. 1781
    • Choe, M.1
  • 14
    • 0031378861 scopus 로고    scopus 로고
    • A 12-b, 60-MS/s cascaded folding and interpolating ADC
    • Dec
    • P. Vorenkamp et al., "A 12-b, 60-MS/s cascaded folding and interpolating ADC," JSSC, vol. 32, pp. 1876-1886, Dec. 1997.
    • (1997) JSSC , vol.32 , pp. 1876-1886
    • Vorenkamp, P.1
  • 15
  • 16
    • 0030411456 scopus 로고    scopus 로고
    • An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing
    • Dec
    • G. W. Venes and et al., "An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing," JSSC, vol. 31, pp. 1846-1853, Dec. 1996.
    • (1996) JSSC , vol.31 , pp. 1846-1853
    • Venes, G.W.1    and et, al.2
  • 17
    • 0030241345 scopus 로고    scopus 로고
    • CMOS folding A/D converters with currentmode interpolation
    • Sept
    • M. P. Flynn and et al., "CMOS folding A/D converters with currentmode interpolation," JSSC, vol. 31, pp. 1248-1257, Sept. 1996.
    • (1996) JSSC , vol.31 , pp. 1248-1257
    • Flynn, M.P.1    and et, al.2
  • 18
    • 0029510025 scopus 로고
    • A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter
    • Dec
    • B. Nauta and et al., "A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter," JSSC, vol. 30, pp. 1302-1308, Dec. 1995.
    • (1995) JSSC , vol.30 , pp. 1302-1308
    • Nauta, B.1    and et, al.2
  • 19
    • 0018713960 scopus 로고
    • A high-speed 7 bit A/D converter
    • Jun
    • R. J. Van De Plassche et al., "A high-speed 7 bit A/D converter," JSSC, vol. 14, pp. 938, Jun. 1979.
    • (1979) JSSC , vol.14 , pp. 938
    • Van De Plassche, R.J.1
  • 20
    • 10444278085 scopus 로고    scopus 로고
    • 2 0.13-μm CMOS
    • Dec
    • 2 0.13-μm CMOS," JSSC, vol. 39, pp. 2116-2125, Dec. 2004.
    • (2004) JSSC , vol.39 , pp. 2116-2125
    • Mulder, J.1
  • 21
    • 0035273821 scopus 로고    scopus 로고
    • A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V
    • Mar
    • R. C. Taft et al., "A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V," JSSC, vol. 36, pp. 331, Mar. 2001.
    • (2001) JSSC , vol.36 , pp. 331
    • Taft, R.C.1
  • 22
    • 0033281188 scopus 로고    scopus 로고
    • A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist
    • Dec
    • B. P. Brandt et al., "A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist," JSSC, vol. 34, pp. 1788-1795, Dec. 1999.
    • (1999) JSSC , vol.34 , pp. 1788-1795
    • Brandt, B.P.1
  • 23
    • 0029488307 scopus 로고
    • Mixed-mode subranging CMOS A/D converter
    • Dec
    • M. Yotsuyanagi et al., "Mixed-mode subranging CMOS A/D converter," JSSC, vol. 30, pp. 1533-1537, Dec. 1995.
    • (1995) JSSC , vol.30 , pp. 1533-1537
    • Yotsuyanagi, M.1
  • 24
    • 0343930350 scopus 로고
    • A two-residue architecture for multistage ADCs
    • C. Mangelsdorf et al., "A two-residue architecture for multistage ADCs," ISSCC, 1993, pp. 64-65.
    • (1993) ISSCC , pp. 64-65
    • Mangelsdorf, C.1
  • 25
    • 0027887674 scopus 로고
    • A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC
    • Dec
    • K. Kusumoto et al., "A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC," JSSC, vol. 28, pp. 1200-1206, Dec. 1993.
    • (1993) JSSC , vol.28 , pp. 1200-1206
    • Kusumoto, K.1
  • 26
    • 0036045284 scopus 로고    scopus 로고
    • A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOS
    • M. Clara et al., "A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOS," CICC, 2002, pp. 437-440.
    • (2002) CICC , pp. 437-440
    • Clara, M.1
  • 27
    • 0035693616 scopus 로고    scopus 로고
    • 2 with mixed-signal chopping and calibration
    • Dec
    • 2 with mixed-signal chopping and calibration," JSSC, vol. 36, pp. 1859-1867, Dec. 2001.
    • (2001) JSSC , vol.36 , pp. 1859-1867
    • van der Ploeg, H.1
  • 28
    • 0034480240 scopus 로고    scopus 로고
    • A 3.3-V 12-b 50-MS/s ADC in 0.6-μm CMOS with over 80-dB SFDR
    • Dec
    • H. Pan et al., "A 3.3-V 12-b 50-MS/s ADC in 0.6-μm CMOS with over 80-dB SFDR," JSSC, vol. 35, pp. 1769-1780, Dec. 2000.
    • (2000) JSSC , vol.35 , pp. 1769-1780
    • Pan, H.1
  • 29
    • 0031073822 scopus 로고    scopus 로고
    • A 12 b 128 MS/s ADC with 0.05 LSB DNL
    • R. Jewett et al., "A 12 b 128 MS/s ADC with 0.05 LSB DNL," ISSCC, 1997, pp. 138-139.
    • (1997) ISSCC , pp. 138-139
    • Jewett, R.1
  • 30
    • 28144434203 scopus 로고    scopus 로고
    • A 30mW 8b 200MS/S Pipelined CMOS ADC Using a Switched-Opamp Technique
    • H. Kim, "A 30mW 8b 200MS/S Pipelined CMOS ADC Using a Switched-Opamp Technique," ISSCC, 2005, pp. 284-285.
    • (2005) ISSCC , pp. 284-285
    • Kim, H.1
  • 31
    • 2442676922 scopus 로고    scopus 로고
    • A 96dB SFDR SOMS/s digitally enhanced CMOS pipeline A/D converter
    • K. Nair et al., "A 96dB SFDR SOMS/s digitally enhanced CMOS pipeline A/D converter," ISSCC, 2004, pp. 456-457.
    • (2004) ISSCC , pp. 456-457
    • Nair, K.1
  • 32
    • 2442664443 scopus 로고    scopus 로고
    • A 15b 20MS/s CMOS pipelined ADC with digital background calibration
    • L. Hung-Chih et al., "A 15b 20MS/s CMOS pipelined ADC with digital background calibration," ISSCC, 2004, pp. 454-455.
    • (2004) ISSCC , pp. 454-455
    • Hung-Chih, L.1
  • 33
    • 2442650652 scopus 로고    scopus 로고
    • A 12b 80MS/s pipelined ADC with bootstrapped digital calibration
    • C. R. Grace et al., "A 12b 80MS/s pipelined ADC with bootstrapped digital calibration," ISSCC, 2004, pp. 460-461.
    • (2004) ISSCC , pp. 460-461
    • Grace, C.R.1
  • 34
    • 2542460411 scopus 로고    scopus 로고
    • A 1.2V 220MS/s 10b pipeline ADC implemented in 0.13μm digital CMOS
    • B. Hernes et al., "A 1.2V 220MS/s 10b pipeline ADC implemented in 0.13μm digital CMOS," ISSCC, 2004, pp. 256-257.
    • (2004) ISSCC , pp. 256-257
    • Hernes, B.1
  • 35
    • 10444270157 scopus 로고    scopus 로고
    • A digitally enhanced 1.8-V 15-bit 40-MS/s CMOS pipelined ADC
    • Dec
    • E. Siragusa et al., "A digitally enhanced 1.8-V 15-bit 40-MS/s CMOS pipelined ADC," JSSC, vol. 39, pp. 2126-2138, Dec. 2004.
    • (2004) JSSC , vol.39 , pp. 2126-2138
    • Siragusa, E.1
  • 36
    • 10444266682 scopus 로고    scopus 로고
    • A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR
    • Dec
    • Y. Chiu et al., "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," JSSC, vol. 39, pp. 2139-2151, Dec. 2004.
    • (2004) JSSC , vol.39 , pp. 2139-2151
    • Chiu, Y.1
  • 37
    • 4544256290 scopus 로고    scopus 로고
    • A 600MS/s, 5-bit pipelined analog-to-digital converter for serial-link applications
    • A. Varzaghani et al., "A 600MS/s, 5-bit pipelined analog-to-digital converter for serial-link applications," VLSI Symposium, 2004, pp. 276-279.
    • (2004) VLSI Symposium , pp. 276-279
    • Varzaghani, A.1
  • 38
    • 4644297975 scopus 로고    scopus 로고
    • Least mean square adaptive digital background calibration of pipelined analog-to-digital converters
    • Jan
    • Y. Chiu et al., "Least mean square adaptive digital background calibration of pipelined analog-to-digital converters," TCAS-I, vol. 51, pp. 38-46, Jan. 2004.
    • (2004) TCAS-I , vol.51 , pp. 38-46
    • Chiu, Y.1
  • 39
    • 0242696104 scopus 로고    scopus 로고
    • A 12-bit 20-MS/s pipelined ADC with nested digital background calibration
    • X. Wang et al., "A 12-bit 20-MS/s pipelined ADC with nested digital background calibration," CICC, 2003, pp. 409-412.
    • (2003) CICC , pp. 409-412
    • Wang, X.1
  • 40
    • 0348233280 scopus 로고    scopus 로고
    • A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
    • Dec
    • B. Murmann et al., "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," JSSC, vol. 38, p. 2040, Dec. 2003.
    • (2003) JSSC , vol.38 , pp. 2040
    • Murmann, B.1
  • 41
    • 0346972345 scopus 로고    scopus 로고
    • A 69-mW 10-bit 80-MS/s pipelined CMOS ADC
    • Dec
    • B.-M. Min et al., "A 69-mW 10-bit 80-MS/s pipelined CMOS ADC," JSSC, vol. 38, pp. 2031-2039, Dec. 2003.
    • (2003) JSSC , vol.38 , pp. 2031-2039
    • Min, B.-M.1
  • 42
    • 0242443698 scopus 로고    scopus 로고
    • A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS technique
    • J. Li et al., "A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS technique," CICC, 2003, pp. 413-416.
    • (2003) CICC , pp. 413-416
    • Li, J.1
  • 43
    • 0036106114 scopus 로고    scopus 로고
    • A 16mW 30MSample/s 10b pipelined ADC using a pseudo-differential architecture
    • D. Miyazaki et al., "A 16mW 30MSample/s 10b pipelined ADC using a pseudo-differential architecture," ISSCC, 2002, pp. 174-175.
    • (2002) ISSCC , pp. 174-175
    • Miyazaki, D.1
  • 44
    • 0035693618 scopus 로고    scopus 로고
    • A 3-V 340-mW 14-b 75-MS/s CMOS ADC with 85-dB SFDR at Nyquist input
    • Dec
    • W. Yang et al., "A 3-V 340-mW 14-b 75-MS/s CMOS ADC with 85-dB SFDR at Nyquist input," JSSC, vol. 36, p. 1931, Dec. 2001.
    • (2001) JSSC , vol.36 , pp. 1931
    • Yang, W.1
  • 45
    • 0035111581 scopus 로고    scopus 로고
    • 1-V 9-bit pipelined switched-opamp ADC
    • Jan
    • M. Waltari et al., " 1-V 9-bit pipelined switched-opamp ADC," JSSC, vol. 36, pp. 129-134, Jan. 2001.
    • (2001) JSSC , vol.36 , pp. 129-134
    • Waltari, M.1
  • 46
    • 0035473398 scopus 로고    scopus 로고
    • An 8-bit 80-Msample/s pipelined ADC with background calibration
    • Oct
    • J. Ming et al., "An 8-bit 80-Msample/s pipelined ADC with background calibration," JSSC, vol. 36, pp. 1489-1497, Oct. 2001.
    • (2001) JSSC , vol.36 , pp. 1489-1497
    • Ming, J.1
  • 47
    • 0034428237 scopus 로고    scopus 로고
    • A 12b 65MS/S CMOS ADC with 82 dB SFDR at 120 MHz
    • L. Singer et al., "A 12b 65MS/S CMOS ADC with 82 dB SFDR at 120 MHz," ISSCC, 2000, pp. 38-39.
    • (2000) ISSCC , pp. 38-39
    • Singer, L.1
  • 48
    • 0032664038 scopus 로고    scopus 로고
    • A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
    • May
    • M. Abo et al., "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," JSSC, vol. 34, pp. 599-606, May 1999.
    • (1999) JSSC , vol.34 , pp. 599-606
    • Abo, M.1
  • 49
    • 0032316909 scopus 로고    scopus 로고
    • A continuously calibrated 12-b, 10-MS/s, 3.3-V ADC
    • Dec
    • J. M. Ingino et al., "A continuously calibrated 12-b, 10-MS/s, 3.3-V ADC," JSSC, vol. 33, pp. 1920-1931, Dec. 1998.
    • (1998) JSSC , vol.33 , pp. 1920-1931
    • Ingino, J.M.1
  • 50
    • 0031359733 scopus 로고    scopus 로고
    • A 15-b, 5-MS/s low-spurious CMOS ADC
    • Dec
    • S.-U. Kwak et al., "A 15-b, 5-MS/s low-spurious CMOS ADC," JSSC, vol. 32, pp. 1866-1875, Dec. 1997.
    • (1997) JSSC , vol.32 , pp. 1866-1875
    • Kwak, S.-U.1
  • 51
    • 0030190925 scopus 로고    scopus 로고
    • Area-efficient self-calibration technique for pipelined algorithmic A/D converters
    • July
    • K. Nagaraj, "Area-efficient self-calibration technique for pipelined algorithmic A/D converters," TCAS-II, vol. 43, p. 540, July 1996.
    • (1996) TCAS-II , vol.43 , pp. 540
    • Nagaraj, K.1
  • 52
    • 0030394188 scopus 로고    scopus 로고
    • A 200-mW, 1-MS/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller
    • Dec
    • M. K. Mayes et al., "A 200-mW, 1-MS/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller," JSSC, vol. 31, pp. 1862-1872, Dec. 1996.
    • (1996) JSSC , vol.31 , pp. 1862-1872
    • Mayes, M.K.1
  • 53
    • 0030106088 scopus 로고    scopus 로고
    • A power optimized 13-b 5-MS/s pipelined ADC in 1.2-μm CMOS
    • Mar
    • D. W. Cline et al., "A power optimized 13-b 5-MS/s pipelined ADC in 1.2-μm CMOS," JSSC, vol. 31, pp. 294-303, Mar. 1996.
    • (1996) JSSC , vol.31 , pp. 294-303
    • Cline, D.W.1
  • 54
    • 0029293925 scopus 로고
    • A 13-b 10-MS/s ADC digitally calibrated with oversampling delta-sigma converter
    • Apr
    • T.-H. Shu et al., "A 13-b 10-MS/s ADC digitally calibrated with oversampling delta-sigma converter," JSSC, vol. 30, pp. 443-452, Apr. 1995.
    • (1995) JSSC , vol.30 , pp. 443-452
    • Shu, T.-H.1
  • 55
    • 0029269932 scopus 로고
    • A 10 b, 20 MS/s, 35 mW pipeline A/D converter
    • Mar
    • T. B. Cho et al., "A 10 b, 20 MS/s, 35 mW pipeline A/D converter," JSSC, vol. 30, pp. 166-172, Mar. 1995.
    • (1995) JSSC , vol.30 , pp. 166-172
    • Cho, T.B.1
  • 56
    • 0027853599 scopus 로고
    • A 15-b 1-MS/s digitally self-calibrated pipeline ADC
    • Dec
    • N. Karanicolas et al., "A 15-b 1-MS/s digitally self-calibrated pipeline ADC," JSSC, vol. 28, pp. 1207-1215, Dec. 1993.
    • (1993) JSSC , vol.28 , pp. 1207-1215
    • Karanicolas, N.1
  • 57
    • 0026836960 scopus 로고
    • A 10-b 20-MS/s analog-to-digital converter
    • Mar
    • S. H. Lewis et al., "A 10-b 20-MS/s analog-to-digital converter," JSSC, vol. 27, pp. 351-358, Mar. 1992.
    • (1992) JSSC , vol.27 , pp. 351-358
    • Lewis, S.H.1
  • 58
    • 0026999467 scopus 로고
    • Digital-domain calibration of multistep analog-to-digital converters
    • Dec
    • S.-H. Lee et al., "Digital-domain calibration of multistep analog-to-digital converters," JSSC, vol. 27, pp. 1679-1688, Dec. 1992.
    • (1992) JSSC , vol.27 , pp. 1679-1688
    • Lee, S.-H.1
  • 59
    • 0026141224 scopus 로고
    • A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS
    • Apr
    • Y.-M. Lin et al., "A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS," JSSC, vol. 26, pp. 628-636, Apr. 1991.
    • (1991) JSSC , vol.26 , pp. 628-636
    • Lin, Y.-M.1
  • 60
    • 2442657679 scopus 로고    scopus 로고
    • A 150MS/s 8b 71mW time-interleaved ADC in 0.18μm CMOS
    • S. Limotyrakis et al., "A 150MS/s 8b 71mW time-interleaved ADC in 0.18μm CMOS," ISSCC, 2004, pp. 258-259.
    • (2004) ISSCC , pp. 258-259
    • Limotyrakis, S.1
  • 61
    • 2442692681 scopus 로고    scopus 로고
    • A 6b 600MHz 10mW ADC array in digital 90nm CMOS
    • Draxelmayr, "A 6b 600MHz 10mW ADC array in digital 90nm CMOS," ISSCC, 2004, pp. 264-265.
    • (2004) ISSCC , pp. 264-265
    • Draxelmayr1
  • 62
    • 2442644802 scopus 로고    scopus 로고
    • A 20GS/S 8b ADC with a 1MB memory in 0.18μmCMOS
    • K. Poulton et al., "A 20GS/S 8b ADC with a 1MB memory in 0.18μmCMOS," ISSCC, 2003, pp. 318-319.
    • (2003) ISSCC , pp. 318-319
    • Poulton, K.1
  • 63
    • 0038645290 scopus 로고    scopus 로고
    • A 2GS/S 6b ADC in 0.18μm CMOS
    • X. Jiang et al., "A 2GS/S 6b ADC in 0.18μm CMOS," ISSCC, 2003, pp. 322-323.
    • (2003) ISSCC , pp. 322-323
    • Jiang, X.1
  • 64
    • 0036912842 scopus 로고    scopus 로고
    • A 10-b 120-MS/s time-interleaved analog-to-digital converter with digital background calibration
    • Dec
    • S. M. Jamal et al., "A 10-b 120-MS/s time-interleaved analog-to-digital converter with digital background calibration," JSSC, vol. 37, pp. 1618-1627, Dec. 2002.
    • (2002) JSSC , vol.37 , pp. 1618-1627
    • Jamal, S.M.1
  • 65
    • 0033281382 scopus 로고    scopus 로고
    • GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link
    • W. Ellersick et al., "GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link," VLSI Symposium, 1999, pp. 49-52.
    • (1999) VLSI Symposium , pp. 49-52
    • Ellersick, W.1
  • 66
    • 0032313025 scopus 로고    scopus 로고
    • A digital background calibration technique for time-interleaved analog-to-digital converters
    • Dec
    • D. Fu et al., "A digital background calibration technique for time-interleaved analog-to-digital converters," JSSC, vol. 33, pp. 1904-1911, Dec. 1998.
    • (1998) JSSC , vol.33 , pp. 1904-1911
    • Fu, D.1
  • 67
    • 0032308947 scopus 로고    scopus 로고
    • An analog background calibration technique for time-interleaved analog-to-digital converters
    • Dec
    • K. C. Dyer et al., "An analog background calibration technique for time-interleaved analog-to-digital converters," JSSC, vol. 33, pp. 1912-1919, Dec. 1998.
    • (1998) JSSC , vol.33 , pp. 1912-1919
    • Dyer, K.C.1
  • 68
    • 0031102957 scopus 로고    scopus 로고
    • A 250-mW, 8-b, 52-MS/s parallel-pipelined A/D converter with reduced number of amplifiers
    • Mar
    • K. Nagaraj et al., "A 250-mW, 8-b, 52-MS/s parallel-pipelined A/D converter with reduced number of amplifiers," JSSC, vol. 32, pp. 312-320, Mar. 1997.
    • (1997) JSSC , vol.32 , pp. 312-320
    • Nagaraj, K.1
  • 69
    • 0029267888 scopus 로고
    • An 85 mW, 10 b, 40 MS/s CMOS parallel-pipelined ADC
    • Mar
    • K. Nakamura et al., "An 85 mW, 10 b, 40 MS/s CMOS parallel-pipelined ADC," JSSC, vol. 30, pp. 173-183, Mar. 1995.
    • (1995) JSSC , vol.30 , pp. 173-183
    • Nakamura, K.1
  • 70
    • 0027576932 scopus 로고
    • An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS
    • Apr
    • CSG. Conroy et al., "An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS," JSSC, vol. 28, pp. 447-454, Apr. 1993.
    • (1993) JSSC , vol.28 , pp. 447-454
    • Conroy, C.S.G.1
  • 71
    • 0019265826 scopus 로고
    • Time interleaved converter arrays
    • Jun
    • W. C. Black et al., "Time interleaved converter arrays," JSSC, vol. 15, pp. 1022-1029, Jun. 1980.
    • (1980) JSSC , vol.15 , pp. 1022-1029
    • Black, W.C.1
  • 72
    • 28144441372 scopus 로고    scopus 로고
    • A 100dB SNR 2.5MS/S Output Data Rate AS ADC
    • R. Brewer, "A 100dB SNR 2.5MS/S Output Data Rate AS ADC," ISSCC, 2005, pp. 172-173.
    • (2005) ISSCC , pp. 172-173
    • Brewer, R.1
  • 73
    • 28144436399 scopus 로고    scopus 로고
    • An 80MHz 4x Oversampled Cascaded AX-Pipelined ADC with 75dB DR and 87dB SFDR
    • A. Bosi, "An 80MHz 4x Oversampled Cascaded AX-Pipelined ADC with 75dB DR and 87dB SFDR," ISSCC, 2005, pp. 174-175.
    • (2005) ISSCC , pp. 174-175
    • Bosi, A.1
  • 74
    • 10444270156 scopus 로고    scopus 로고
    • A continuous-time IA ADC with increased immunity to interferes
    • Dec
    • K. Philips et al., "A continuous-time IA ADC with increased immunity to interferes," JSSC, vol. 39, pp. 2170-2178, Dec. 2004.
    • (2004) JSSC , vol.39 , pp. 2170-2178
    • Philips, K.1
  • 75
    • 10444259730 scopus 로고    scopus 로고
    • A 25-MS/s 14-b 200-mW IA Modulator in 0.18-μm CMOS
    • Dec
    • P. Balmelli et al., "A 25-MS/s 14-b 200-mW IA Modulator in 0.18-μm CMOS," JSSC, vol. 39, pp. 2161-2169, Dec. 2004.
    • (2004) JSSC , vol.39 , pp. 2161-2169
    • Balmelli, P.1
  • 76
    • 0036050041 scopus 로고    scopus 로고
    • Digital techniques for improved AI data conversion
    • J. Silva et al., "Digital techniques for improved AI data conversion," CICC, 2002, pp. 183-190.
    • (2002) CICC , pp. 183-190
    • Silva, J.1
  • 77
    • 0036913625 scopus 로고    scopus 로고
    • A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-333-kHz bandwidth
    • Dec
    • R. Schreier et al., "A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-333-kHz bandwidth," JSSC, vol. 37, pp. 1636-1644, Dec. 2002.
    • (2002) JSSC , vol.37 , pp. 1636-1644
    • Schreier, R.1
  • 78
    • 0036908706 scopus 로고    scopus 로고
    • A 64-MHz clock-rate ∑Δ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency
    • Dec
    • S. K. Gupta et al., "A 64-MHz clock-rate ∑Δ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency," JSSC, vol. 37, pp. 1653-1661, Dec. 2002.
    • (2002) JSSC , vol.37 , pp. 1653-1661
    • Gupta, S.K.1
  • 79
    • 0034478801 scopus 로고    scopus 로고
    • A high-performance multibit Delta-Sigma CMOS ADC
    • Dec
    • Y. Geerts et al., "A high-performance multibit Delta-Sigma CMOS ADC," JSSC, vol. 35, pp. 1829-1840, Dec. 2000.
    • (2000) JSSC , vol.35 , pp. 1829-1840
    • Geerts, Y.1
  • 80
    • 0034479805 scopus 로고    scopus 로고
    • A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8x oversampling ratio
    • Dec
    • Fujimori et al., "A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8x oversampling ratio," JSSC, vol. 35, pp. 1820-1828, Dec. 2000.
    • (2000) JSSC , vol.35 , pp. 1820-1828
    • Fujimori1
  • 81
    • 0033280277 scopus 로고    scopus 로고
    • A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside a sigma-delta modulator loop
    • Dec
    • Namdar et al., "A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside a sigma-delta modulator loop," JSSC, vol. 34, pp. 1765-1776, Dec. 1999.
    • (1999) JSSC , vol.34 , pp. 1765-1776
    • Namdar1
  • 82
    • 0032317771 scopus 로고    scopus 로고
    • A 900-mV low-power Delta-Sigma A/D converter with 77-dB dynamic range
    • Dec
    • V. Peluso et al., "A 900-mV low-power Delta-Sigma A/D converter with 77-dB dynamic range," JSSC, vol. 33, pp. 1887-1897, Dec. 1998.
    • (1998) JSSC , vol.33 , pp. 1887-1897
    • Peluso, V.1
  • 83
    • 0031333312 scopus 로고    scopus 로고
    • A cascaded sigma-delta pipeline ADC with 1.25 MHz signal bandwidth and 89 dB SNR
    • Dec
    • T. L. Brooks et al., "A cascaded sigma-delta pipeline ADC with 1.25 MHz signal bandwidth and 89 dB SNR," JSSC, vol. 32, pp. 1896-1906, Dec. 1997.
    • (1997) JSSC , vol.32 , pp. 1896-1906
    • Brooks, T.L.1
  • 84
    • 0027876242 scopus 로고
    • Self-calibration techniques for a second-order multibit sigma-delta modulator
    • Dec
    • J. W. Fattaruso et al., "Self-calibration techniques for a second-order multibit sigma-delta modulator," JSSC, vol. 28, pp. 1216-1223, Dec. 1993.
    • (1993) JSSC , vol.28 , pp. 1216-1223
    • Fattaruso, J.W.1
  • 85
    • 0026400093 scopus 로고
    • A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion
    • Dec
    • P. Brandt et al., "A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion," JSSC, vol. 26, pp. 1746-1756, Dec. 1991.
    • (1991) JSSC , vol.26 , pp. 1746-1756
    • Brandt, P.1
  • 86
    • 0024124005 scopus 로고
    • The design of sigma-delta modulation analog-to-digital converters
    • Jun
    • B. E. Boser et al., "The design of sigma-delta modulation analog-to-digital converters," JSSC, vol. 23, pp. 1298-1308, Jun. 1988.
    • (1988) JSSC , vol.23 , pp. 1298-1308
    • Boser, B.E.1
  • 88
    • 4544284883 scopus 로고    scopus 로고
    • 0.9V 12mW 2MSPS algorithmic ADC with 81dB SFDR
    • L. Jipeng et al., "0.9V 12mW 2MSPS algorithmic ADC with 81dB SFDR," VLSI, 2004, pp. 436-439.
    • (2004) VLSI , pp. 436-439
    • Jipeng, L.1
  • 89
    • 18544399632 scopus 로고    scopus 로고
    • A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD
    • Dec
    • O. E. Erdogan et al., "A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD," JSSC, vol. 34, pp. 1812-1820, Dec. 1999.
    • (1999) JSSC , vol.34 , pp. 1812-1820
    • Erdogan, O.E.1
  • 90
    • 0028417146 scopus 로고
    • A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC
    • Apr
    • H.-S. Lee, "A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC," JSSC, vol. 29, pp. 509-515, Apr., 1994.
    • (1994) JSSC , vol.29 , pp. 509-515
    • Lee, H.-S.1
  • 91
    • 0021616937 scopus 로고
    • A self-calibrating 15-bit CMOS ADC
    • Jun
    • H.-S. Lee et al., "A self-calibrating 15-bit CMOS ADC," JSSC, vol. 19, pp. 813-819, Jun. 1984.
    • (1984) JSSC , vol.19 , pp. 813-819
    • Lee, H.-S.1
  • 92
    • 0018727884 scopus 로고    scopus 로고
    • B. J. Hosticka, Improvement of the gain of MOS amplifiers, JSSC, sc-14,pp. 1111-1114, Dec. 1979.
    • B. J. Hosticka, "Improvement of the gain of MOS amplifiers," JSSC, vol. sc-14,pp. 1111-1114, Dec. 1979.
  • 93
    • 0025386508 scopus 로고
    • A high-swing, high-impedance MOS cascode Circuit
    • Feb
    • E. Sackinger et al., "A high-swing, high-impedance MOS cascode Circuit," JSSC, vol. 25, pp. 289-298, Feb. 1990.
    • (1990) JSSC , vol.25 , pp. 289-298
    • Sackinger, E.1
  • 94
    • 0025568946 scopus 로고
    • A fast-settling CMOS op amp for SC circuits with 90-dB DC gain
    • Dec
    • K. Bult et al., "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain," JSSC, vol. 25, pp. 1379-1384, Dec. 1990.
    • (1990) JSSC , vol.25 , pp. 1379-1384
    • Bult, K.1
  • 95
    • 0032272385 scopus 로고    scopus 로고
    • Transistor matching in analog CMOS applications
    • M. J. M. Pelgrom et al., "Transistor matching in analog CMOS applications," IEDM, 1998, pp. 915-918.
    • (1998) IEDM , pp. 915-918
    • Pelgrom, M.J.M.1
  • 96
    • 0024754187 scopus 로고
    • Matching properties of MOS transistors
    • May
    • M. J. M. Pelgrom et al., "Matching properties of MOS transistors," JSSC, vol. 24, pp. 1433-1439, May 1989.
    • (1989) JSSC , vol.24 , pp. 1433-1439
    • Pelgrom, M.J.M.1
  • 97
    • 0028513902 scopus 로고
    • Threshold voltage mismatch in short-channel MOS transistors
    • M. Steyaert et al., "Threshold voltage mismatch in short-channel MOS transistors," Electronics Letters, vol. 30, pp. 1546-1548, 1994.
    • (1994) Electronics Letters , vol.30 , pp. 1546-1548
    • Steyaert, M.1
  • 99
    • 0033879027 scopus 로고    scopus 로고
    • MOS transistor modeling for RF IC design
    • Feb
    • C. Enz et al., "MOS transistor modeling for RF IC design," JSSC, vol. 35, pp. 186-201, Feb. 2000.
    • (2000) JSSC , vol.35 , pp. 186-201
    • Enz, C.1
  • 100
    • 0022811203 scopus 로고
    • High-frequency noise measurements on FETs with small dimensions
    • Nov
    • A. A. Abidi, "High-frequency noise measurements on FETs with small dimensions," TED, pp. 1801-1805, Nov. 1986.
    • (1986) TED , pp. 1801-1805
    • Abidi, A.A.1
  • 101
    • 0036503668 scopus 로고    scopus 로고
    • Capacity limits and matching properties of integrated capacitors
    • Mar
    • R. Aparicio, "Capacity limits and matching properties of integrated capacitors," JSSC, vol. 37, pp. 384-393, Mar. 2002.
    • (2002) JSSC , vol.37 , pp. 384-393
    • Aparicio, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.