A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 5, 1999, Pages 599-606

  Abo, Andrew M ^b   Gray, Paul R ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Analog to digital; Low voltage; Reliability

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC DISTORTION; RELIABILITY; SIGNAL TO NOISE RATIO;

LOW VOLTAGE DEVICES;

ANALOG TO DIGITAL CONVERSION;

EID: 0032664038     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.760369     Document Type: Article

References (23)

1. Semiconductor Industry Association. (1997). The national technology roadmap for semiconductors. [Online]. Available WWW: http://www.sematech.org/.
2. B. Davari, R. Dennard, and G. Shahidi, "CMOS scaling for high performance and low power - the next ten years," Proc. IEEE, vol. 83, pp. 595-606, Apr. 1995.
3. ∼tcho/.
4. M. Yotsuyanagi, H. Hasegawa, M. Yamaguchi, and M. Ishida, "A 2 V 10 b 20 Msample/s mixed-mode subranging CMOS A/D converter," in 1995 IEEE Int. Solid-Sate Circuits Conf. Dig. Tech. Papers, San Francisco, CA, 1995, pp. 282-283.
5. H. Hasegawa, M. Yotsuyanagi, M. Satoh, and S. Kishi, "A 1.5 V 8b 8 mW BiCMOS video A/D converter," in 1996 IEEE Int. Solid-Sate Circuits Conf. Dig. Tech. Papers, San Francisco, CA, 1996, pp. 322-323.
6. F. Maloberti, F. Francesconi, P. Malcovati, and O. J. A. P. Nys, "Design considerations on low-voltage low-power data converters," IEEE Trans. Circuits Syst. I, vol. 42, pp. 853-863, Nov. 1995.
7. R. Castello, F. Montecchi, F. Rezzi, and A. Baschirotto, "Low-voltage analog filters," IEEE Trans. Circuits Syst. I, vol. 42, pp. 827-40, Nov. 1995.
8. J.-T. Wu, Y.-H. Chang, and K.-L. Chang, "1.2V CMOS switched-capacitor circuits," in 1996 IEEE Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, Feb. 1996, pp. 388-389.
9. Y.-M. Lin, B. Kim, and P. R. Gray, "A 13-b, 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS," IEEE J. Solid-Sate Circuits, vol. 26, pp. 628-636, Apr. 1991.
10. B. K. Ahuja, "An improved frequency compensation technique for CMOS operational amplifiers," IEEE J. Solid-Sate Circuits, vol. SC-18, pp. 629-33, Dec. 1983.
11. D. B. Ribner and M. A. Copeland, "Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range," IEEE J. Solid-Sate Circuits, vol. SC-19, pp. 919-25, Dec. 1984.
12. C. A. Laber, C. F. Rahim, S. F. Dreyer, G. T. Uehara, P. T. Kwok, and P. R. Gray, "Design considerations for a high-performance 3-μm CMOS analog standard-cell library," IEEE J. Solid-Sate Circuits, vol. SC-22, pp. 181-9, Apr. 1987.
13. Y.-M. Lin, "Performance limitations on high-resolution video-rate analog-to-digital interfaces," Ph.D. dissertation, Univ. of California, Berkeley, UCB/ERL M90/55, June 1990.
14. R. Moazzami and C. Hu, "Projecting oxide reliability and optimizing burn-in," IEEE Trans. Electron Devices, vol. 37, pp. 1643-1650, July 1990.
15. C. Hu, "Gate oxide scaling limits and projection," in IEDM Tech. Dig., San Francisco, CA, 1996, pp. 319-322.
16. _, "Ultra-large-scale integration device scaling and reliability," J. Vac. Sci. Technol. B, vol. 12, no. 6, pp. 3237-41, Nov./Dec. 1994.
17. J. L. Gorecki, "Dynamic input sampling switch for CDAC's," U.S. Patent 5084634, Jan. 28, 1992; see also [Online]. Available WWW: http://www.patents.ibm.com.
18. M. de Wit, "Sample and hold circuit and methods," U.S. Patent, 5170075, Dec. 8, 1992; see also [Online]. Available WWW: http://www.patents.ibm.com.
19. J. R. Naylor and M. A. Shill, "Bootstrapped FET sampling switch," U.S. Patent 5172019, Dec. 15, 1992; see also [Online]. Available WWW: http://www.patents.ibm.com.
20. D. J. Sauer, "Constant impedance sampling switch for an analog to digital converter," U.S. Patent, 5500612, Mar. 19, 1996; see also [Online]. Available WWW: http://www.patents.ibm.com.
21. T. L. Brooks, D. H. Robertson, D. F. Kelly, and A. Del Muro, "A 16b sigma data pipeline ADC with 2.5 MHz output data-rate," 1997 IEEE Int. Solid-Sate Circuits Conf. Dig. Tech. Papers, San Francisco, CA, 1997, pp. 208-209.
22. E. R. Minami, S. B. Kuusinen, E. Rosenbaum, P. K. Ko, and C. Hu, "Circuit-level simulation of TDDB failure in digital CMOS circuits," IEEE Trans. Semiconduct. Manufact., vol. 8, pp. 370-374, Aug. 1995.
23. C. Hu, "IC reliability simulation," IEEE J. Solid-Sate Circuits, vol. 27, pp. 241-246, Mar. 1992.