A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 296-297

  Verbruggen, Bob ^a,b   Craninckx, Jan ^a   Kuijk, Maarten ^b   Wambacq, Piet ^a,b   Van Der Plas, Geert ^a  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CMOS; INPUT CAPACITANCE; INTERLEAVED CONVERTERS; LOW POWER; LOW RESOLUTION; PIPELINED ADCS;

FREQUENCY BANDS;

CALIBRATION;

EID: 77952217397     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433925     Document Type: Conference Paper

References (5)

1. M. Miyahara, et al., "A low-noise self-calibrating dynamic comparator for high-speed ADCs", Asian Solid-State Circuits Conf., pp. 554-557, Nov. 2008.
2. G. Van der Plas, B. Verbruggen, "A 150 MS/s 133 μW 7 bit ADC in 90 nm Digital CMOS", IEEE J. Solid State Circuits, vol. 43, no. 12, pp. 2631-2640, Dec. 2008.
3. A. Nazemi, "A 10.3Gs/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS", Dig. Symp. VLSI Circuits, pp. 14-15, June 2008.
4. G. Van der Plas, S. Decoutere, S. Donnay, "A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process", ISSCC Dig. Tech. Papers, pp. 566-567, Feb. 2006.
5. P. Nuzzo, et al., "Efficient calibration through statistical behavioral modeling of a high-speed low-power ADC", Proc. of PRIME, pp. 297-300, Jun. 2006.