A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 337-340

  Bogue, Ivan ^a   Flynn, Michael P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; INTEGRATED CIRCUITS;

ANALOG ACCURACIES; DIE AREA; DIGITAL CMOS; SAMPLING RATES; SIGNAL PATHS; UNCALIBRATED; ZERO-CROSSINGS;

CALIBRATION;

EID: 70449500312     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405747     Document Type: Conference Paper

References (4)

1. R. C. Taft, C. A. Menkus, M. R. Tursi, O. Hidri and V. Pons, "A 1. 8-V 1. 6-GSample/s 8-b self-calibrating folding ADC with 7. 26 ENOB at Nyquist frequency", IEEE J. Solid-State Circuits, Vol. 39, Issue 12, Dec. 2004 Page(s):2107-2115
2. B. Murmann and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification", IEEE J. Solid-State Circuits, Vol. 38, Issue 12, Dec 2003 Page(s):2040-2050
3. C. Donovan and M. P. Flynn, "A 'digital' 6-bit ADC in 0. 25m CMOS", IEEE J. Solid-State Circuits, Vol. 37, Issue 3, March 2002 Page(s): 432-437
4. A. G. W. Venes and R. J. van-de-Plassche, "An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing", IEEE J. Solid-State Circuits, Vol. 31, Issue 12, Dec. 1996 Page(s):1846-1853