A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 12, 2004, Pages 2126-2138

  Siragusa, Eric ^a   Galton, Ian ^b  

^a ANALOG DEVICES INC   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Analog to digital conversion; Calibration; Mixed analog digital integrated circuits (ICs)

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; CALIBRATION; DIGITAL SIGNAL PROCESSING; DIGITAL TO ANALOG CONVERSION; ERROR ANALYSIS; SIGNAL TO NOISE RATIO;

ASYMMETRIC CLOCKING; GAIN ERRORS; MIXED ANALOG-DIGITAL INTEGRATED CIRCUITS (IC); SIGNAL SAMPLING;

CMOS INTEGRATED CIRCUITS;

EID: 10444270157     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.836230     Document Type: Conference Paper

References (29)

1. I. Galton, "Digital cancellation of D/A converter noise in pipelined A/D converters," IEEE Trans. Circuits Syst. II, vol. 47, pp. 185-196, Mar. 2000.
2. E. J. Siragusa and I. Galton, "Gain error correction technique for pipelined analogue-to-digital converters," Electron. Lett., vol. 36, no. 7, pp. 617-618, Mar. 2000.
3. |3] E. Siragusa and I. Galton, "A digitally enhanced 1.8 V 15 b 40 MS/s CMOS pipelined ADC," in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 452-453.
4. C. Grace, P. Hurst, and S. Lewis, "A 12 b 80 MS/s pipelined ADC with bootstrapped digital calibration," in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 460-461.
5. H.-S. Lee, D. A. Hodges, and P. R. Gray, "A self-calibrating 15-bit CMOS A/D converter," IEEE J. Solid-State Circuits, vol. SSC-19, pp. 813-819, Dec. 1984.
6. A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, "A 15-b 1-MSample/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, vol. 28, pp. 1207-1215, Dec. 1993.
7. L. Singer, S. Ho, M. Timko, and D. Kelly, "A 12-b 65-Msample/s CMOS ADC with 82-dB SFDR at 120 MHz," in ISSCC Dig. Tech. Papers, Feb. 2000, pp. 38-39.
8. B. Murmann and B. E. Boser, "A 12 b 75 MS/s pipelined ADC using open-loop residue amplification," in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 328-329.
9. J. Ingino Jr. and B. Wooley, "A continuously-calibrated 10 MSample/ s 12 b 3.3 V ADC," in ISSCC Dig. Tech. Papers, Feb. 1998, pp. 144-145.
10. B.-S. Song, M. Tompsett, and K. Lakshmikumar,"A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter," IEEE J. Solid-State Circuits, vol. 23, pp. 1324-1333, Dec. 1988.
11. H.-S. Chen, B.-S. Song, and K. Bacrania, "A 14-b 20-MSample/s CMOS pipelined ADC," IEEE J. Solid-State Circuits, vol. SSC-36, pp. 997-1001, Dec. 1987.
12. Y. Chiu, P. Gray, and B. Nikolic, "A 1.8 V 14 b 10 MS/s pipelined ADC in 0.18 μm CMOS with 99 dB SFDR," in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 458-459.
13. S.-U. Kwak, B.-S. Song, and K. Bacrania. "A 15-b, 5-Msample/S low-spurious CMOS ADC," IEEE J. Solid-State Circuits, vol. 32, pp. 1866-1875, Dec. 2001.
14. P. C. Yu and H.-S. Lee, "A 2.5 V 12 b 5 Msample/s pipelined CMOS ADC," IEEE J. Solid-State Circuits, vol. 31, pp. 1854-1861, Dec. 1996.
15. R. Jewett, K. Poulton, K.-C. Hsieh, and J. Doernberg, "A 12 b 128 MSample/s ADC with 0.05LSB DNL," in ISSCC Dig. Tech. Papers, Feb. 1997, pp. 138-139.
16. S.-T. Ryu, S. Ray, B.-S. Song, G.-H. Cho, and K. Bacrania, "A 14-b linear capacitor self-trimming pipelined ADC," in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 464-465.
17. P. C. Yu, S. Shehata, A. Joharapurkar, P. Chugh, A. Bugeja, X. Du, S. U. Kwak, Y. Papantonopoulous, and T. Kuyel, "A 14 b 40 MSample/s pipelined ADC with DFCA," in ISSCC Dig. Tech. Papers, Feb. 2001, pp. 136-137.
18. J. Ming and S. Lewis, "An 8 b 80 Msample/s pipelined ADC with background calibration," in ISSCC Dig. Tech. Papers, Feb. 2000, pp. 42-43.
19. J. Li and U.-K. Moon, "Background calibration techniques for multistage pipelined ADC's with digital redundancy," IEEE Trans. Circuits Sys. II, vol. 50, pp. 531-538, Sept. 2003.
20. H.-C. Liu, Z.-M. Lee, and J.-T. Wu, "A 15 b 20 MS/s CMOS pipelined ADC with digital background calibration," in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 454-455.
21. K. Nair and R. Harjani, "A 96 dB SFDR 50 MS/s digitally enhanced CMOS pipeline A/D converter," in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 456-457.
22. S. H. Lewis and P. R. Gray, "A pipelined 5-Msample/s 9-bit analog-to-digital converter," IEEE J. Solid-State Circuits, vol. SSC-22, pp. 954-961, Dec. 1987.
23. P. Rombouts and L. Weyten, "Dynamic element matching for pipelined A/D conversion," in Proc. IEEE Int. Conf. Electronics, Circuits and Systems, vol. 2, Sept. 1998, pp. 315-318.
24. A. Fishov, E. Siragusa, J. Welz, E. Fogleman, and I. Gallon, "Segmented mismatch-shaping D/A conversion," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, May 2002, pp. 26-29.
25. I. Gallon, "Spectral shaping of circuit errors in digital-to-analog converters," IEEE Trans. Circuits Svst. II. vol. 44, pp. 808-817, Nov. 1997.
26. [26| I. Mehr and L. Singer, "A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC," IEEE J. Solid-State Circuits, vol. 35, pp. 318-325, Mar. 2000.
27. M. Dessouky and A. Kaiser, "Input switch configuration suitable for rail-to-rail operation of switched opamp circuits," Electron. Lett., vol. 35, pp. 8-10, Jan. 1999.
28. J. Grilo, I. Gallon, K. Wang, and R. Montemayor, "A 12 mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver," IEEE J. Solid-State Circuits, vol. 37, pp. 271-278, Mar. 2002.
29. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, 2nd ed. Reading, MA: Addison-Wesley, 1993.