메뉴 건너뛰기




Volumn 41, Issue 12, 2006, Pages 2658-2668

Comparator-based switched-capacitor circuits for scaled CMOS technologies

Author keywords

A D; ADC; Analog to digital conversion; CBSC; Comparator based switched capacitor circuits; Pipeline; Scaled CMOS; Switched capacitor circuits

Indexed keywords

COMPARATOR BASED SWITCHED CAPACITOR CIRCUIT (CBSC); SCALED CMOS; SIGNAL CIRCUITS; VIRTUAL GROUND CONDITION;

EID: 33845613087     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.884330     Document Type: Conference Paper
Times cited : (220)

References (23)
  • 1
    • 0022313711 scopus 로고
    • Low-voltage operational amplifier with rail-to-rail input and output ranges
    • Dec.
    • J. Huijsing and D. Linebarger, "Low-voltage operational amplifier with rail-to-rail input and output ranges," IEEE J. Solid-State Circuits, vol. 20, no. 6, pp. 1144-1150, Dec. 1985.
    • (1985) IEEE J. Solid-state Circuits , vol.20 , Issue.6 , pp. 1144-1150
    • Huijsing, J.1    Linebarger, D.2
  • 3
    • 0018470554 scopus 로고
    • Dynamic amplifier for MOS technology
    • May
    • M. A. Copeland and J. M. Rabaey, "Dynamic amplifier for MOS technology," Electron. Lett., vol. 15, no. 10, pp. 301-302, May 1979.
    • (1979) Electron. Lett. , vol.15 , Issue.10 , pp. 301-302
    • Copeland, M.A.1    Rabaey, J.M.2
  • 4
    • 0019073388 scopus 로고
    • Dynamic CMOS amplifiers
    • Oct.
    • B. Hosticka, "Dynamic CMOS amplifiers," IEEE J. Solid-State Circuits, vol. SC-15, no. 5, pp. 881-886, Oct. 1980.
    • (1980) IEEE J. Solid-state Circuits , vol.SC-15 , Issue.5 , pp. 881-886
    • Hosticka, B.1
  • 5
    • 0348233247 scopus 로고    scopus 로고
    • Discrete-time parametric amplification based on a three-terminal MOS varactor: Analysis and experimental results
    • Dec.
    • S. Ranganathan and Y. Tsividis, "Discrete-time parametric amplification based on a three-terminal MOS varactor: analysis and experimental results," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2087-2093, Dec. 2003.
    • (2003) IEEE J. Solid-state Circuits , vol.38 , Issue.12 , pp. 2087-2093
    • Ranganathan, S.1    Tsividis, Y.2
  • 6
    • 10444270157 scopus 로고    scopus 로고
    • A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC
    • Dec.
    • E. Siragusa and I. Galton, "A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2126-2138, Dec. 2004.
    • (2004) IEEE J. Solid-state Circuits , vol.39 , Issue.12 , pp. 2126-2138
    • Siragusa, E.1    Galton, I.2
  • 7
    • 0348233280 scopus 로고    scopus 로고
    • A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
    • Dec.
    • B. Murmann and B. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003.
    • (2003) IEEE J. Solid-state Circuits , vol.38 , Issue.12 , pp. 2040-2050
    • Murmann, B.1    Boser, B.2
  • 9
    • 46149143055 scopus 로고
    • An 11 bit, 50 kSample/s CMOS A/D converter cell using a multislope integration technique
    • May
    • J.-G. Chern and A. Abidi, "An 11 bit, 50 kSample/s CMOS A/D converter cell using a multislope integration technique," in Proc. IEEE Custom Integrated Circuits Conf., May 1989, pp. 6.2/1-6.2/4.
    • (1989) Proc. IEEE Custom Integrated Circuits Conf.
    • Chern, J.-G.1    Abidi, A.2
  • 10
    • 23744476511 scopus 로고    scopus 로고
    • A time-based energy-efficient analog-to-digital converter
    • Aug.
    • H. Yang and R. Sarpeshkar, "A time-based energy-efficient analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1590-1601, Aug. 2005.
    • (2005) IEEE J. Solid-state Circuits , vol.40 , Issue.8 , pp. 1590-1601
    • Yang, H.1    Sarpeshkar, R.2
  • 11
    • 84876585410 scopus 로고
    • An 8-channel 16b eharge-to-digital converter for imaging applications
    • Feb.
    • P. Holloway and G. O'Donoghue, "An 8-channel 16b eharge-to-digital converter for imaging applications," in IEEE ISSCC Dig. Tech. Papers, Feb. 1992, pp. 176-177.
    • (1992) IEEE ISSCC Dig. Tech. Papers , pp. 176-177
    • Holloway, P.1    O'Donoghue, G.2
  • 12
    • 2442691458 scopus 로고    scopus 로고
    • A CMOS image sensor with reset level control using dynamic reset current source for noise suppression
    • Feb.
    • K.-H. Lee and E. Yoon, "A CMOS image sensor with reset level control using dynamic reset current source for noise suppression," in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 114-516.
    • (2004) IEEE ISSCC Dig. Tech. Papers , pp. 114-516
    • Lee, K.-H.1    Yoon, E.2
  • 15
    • 0018396999 scopus 로고
    • MOS switched-capacitor filters
    • Jan.
    • R. Brodersen, P. Gray, and D. Hodges, "MOS switched-capacitor filters," Five. IEEE, vol. 67, no. 1, pp. 61-75, Jan. 1979.
    • (1979) Five. IEEE , vol.67 , Issue.1 , pp. 61-75
    • Brodersen, R.1    Gray, P.2    Hodges, D.3
  • 16
    • 0000076149 scopus 로고
    • A switching scheme for switched capacitor filters which reduces the effect of parasitic capacitances associated with switch control terminals
    • Apr.
    • D. G. Haigh and B. Singh, "A switching scheme for switched capacitor filters which reduces the effect of parasitic capacitances associated with switch control terminals," in Proc. IEEE Int. Symp. Circuits and Systems, Apr. 1983, pp. 586-589.
    • (1983) Proc. IEEE Int. Symp. Circuits and Systems , pp. 586-589
    • Haigh, D.G.1    Singh, B.2
  • 17
    • 0022305546 scopus 로고
    • Low-distortion switched-capacitor filter design techniques
    • Dec.
    • K.-L. Lee and R. G. Meyer, "Low-distortion switched-capacitor filter design techniques," IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp. 1103-1113, Dec. 1985.
    • (1985) IEEE J. Solid-state Circuits , vol.SC-20 , Issue.6 , pp. 1103-1113
    • Lee, K.-L.1    Meyer, R.G.2
  • 18
    • 0001217075 scopus 로고
    • A high-speed CMOS comparator for use in an ADC
    • Feb.
    • B. McCarroll, C. Sodini, and H.-S. Lee, "A high-speed CMOS comparator for use in an ADC," IEEE J. Solid-State Circuits, vol. 23, no. 1, pp. 159-165, Feb. 1988.
    • (1988) IEEE J. Solid-state Circuits , vol.23 , Issue.1 , pp. 159-165
    • McCarroll, B.1    Sodini, C.2    Lee, H.-S.3
  • 19
    • 0028698761 scopus 로고
    • Analog-to-digital converter technology comparison
    • Oct.
    • R. Walden, "Analog-to-digital converter technology comparison," in IEEE GaAs IC Symp. Tech. Dig., Oct. 1994, pp. 217-219.
    • (1994) IEEE GaAs IC Symp. Tech. Dig. , pp. 217-219
    • Walden, R.1
  • 20
    • 33847730791 scopus 로고    scopus 로고
    • A 90 nm CMOS 1.2 v 10 b power and speed programmable pipelined ADC with 0.5 pJ/conversion-step
    • Feb.
    • G. Geelen, E. Paulus, D. Simanjuntak, H. Pastoor, and R. Verlinden, "A 90 nm CMOS 1.2 V 10 b power and speed programmable pipelined ADC with 0.5 pJ/conversion-step," in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 214-215.
    • (2006) IEEE ISSCC Dig. Tech. Papers , pp. 214-215
    • Geelen, G.1    Paulus, E.2    Simanjuntak, D.3    Pastoor, H.4    Verlinden, R.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.