A 16b 100-to-160MS/s SiGe BiCMOS pipelined ADC with 100dBFS SFDR

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 294-295

  Payne, Robert ^a   Corsi, Marco ^a   Smith, David ^a   Kaylor, Scott ^a   Hsieh, Daniel ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BASE TRANSCEIVER STATION; HIGH RESOLUTION; HIGH-SPEED; INPUT SIGNAL; MULTI CARRIER; MULTIPLE CHANNELS; PIPELINED ADCS; RF RECEIVER FRONT-END; SAMPLE RATE; SIGE BICMOS; SIGNAL PATHS;

SEMICONDUCTING SILICON;

EID: 77952156023     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433928     Document Type: Conference Paper

References (4)

1. C. Moreland, et al., "A 14-bit 100-Msample/s Subranging ADC," IEEE J. Solid State Circuits, vol. 35, pp. 1791-1798, Dec. 2000.
2. A.M.A. Ali, et al, "A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter," IEEE J. Solid State Circuits, vol. 41, pp. 1846-1855, Aug. 2006.
3. S. Devarajan, et al., "A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC," ISSCC Dig. of Technical Papers, pp. 86-87, Feb. 2009.
4. B. El-Kareh, et al., "A 5V complementary-SiGe BiCMOS technology for high-speed precision analog circuits," Proc. Of the Bipolar/BiCMOS Circuits and Technology Meeting, pp. 211-214, Sep. 2003.