A 300-MS/s 14-bit digital-to-analog converter in logic CMOS

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 5, 2003, Pages 734-740

  Hyde, John ^a   Humes, Todd ^a   Diorio, Chris ^a   Thomas, Mike ^a   Figueroa, Miguel ^b  

^a Impinj   (United States)

^b University of Washington   (United States)

Author keywords

Digital to analog conversion; Floating gate

Indexed keywords

DIGITAL TO ANALOG CONVERSION; ELECTRIC CURRENTS; GATES (TRANSISTOR); LOGIC CIRCUITS; MOSFET DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE;

ELECTRICAL TRIMMING; FLOATING GATE FIELD EFFECT TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 0038529372     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.810049     Document Type: Article

References (10)

1. J. Sevenhans and Z. Chang, "A/D and D/A conversion for telecommunications," IEEE Circuits Devices Mag., vol. 14, pp. 32-42, Jan. 1998.
2. A. Van den Bosch, M. Borreman, M. Steyaert, and W. Sansen, "A 12-b 500-Msample/s current-steering CMOS D/A converter," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2001, pp. 366-367.
3. A. R. Bugeja and B.-S. Song, "A self-trimming 14-b 100-MS/s CMOS DAC," IEEE J. Solid-State Circuits, vol. 35, pp. 1841-1852, Dec. 2000.
4. 2 random walk CMOS DAC," IEEE J. Solid-State Circuits, vol. 34, pp. 1708-1718, Dec. 1999.
5. C. Diorio, S. Mahajan, P. Hasler, B. A. Minch, and C. Mead, "A high-resolution nonvolatile analog memory cell," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 3, 1995, pp. 2233-2236.
6. M. Figueroa, J. Hyde, T. Humes, and C. Diorio, "A floating-gate trimmable high-resolution DAC in standard 0.25-μm CMOS," in Proc. IEEE Nonvolatile Semiconductor Memory Workshop, 2001, pp. 46-47.
7. C. Diorio, "Neurally inspired silicon learning: From synapse transistors to learning arrays," Ph.D. dissertation, Calif. Inst. Technol., Dept. Elec. Eng., Pasadena, CA, 1997.
8. 2," J. Appl. Phys., vol. 40, no. 6, pp. 278-283, 1969.
9. K. Rahimi, C. Diorio, C. Hernandez, and M. D. Brockhausen, "A simulation model for floating-gate MOS synapse transistors," Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, pp. 532-535, 2002.
10. M. J. M. Pelgrom, L. Aad, C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, May 1989.