A 1.2 v 200-MS/s 10-bit folding and interpolating ADC in 0.13-μm CMOS

ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 155-158

  Chen, Yihui ^a   Huang, Qiuting ^a   Burger, Thomas ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); COMPUTER NETWORKS; INTERPOLATION; MULTICARRIER MODULATION; TECHNOLOGY;

AUTO ZEROING; BIT RESOLUTION; CMOS TECHNOLOGIES; EUROPEAN; FOLDING AND INTERPOLATING; OPEN LOOPS; SAMPLE RATE; SOLID-STATE CIRCUITS CONFERENCE; SUPPLY VOLTAGES;

ANALOG TO DIGITAL CONVERSION;

EID: 44849116315     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2007.4430269     Document Type: Conference Paper

References (6)

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2. A. S. Blum, B. H. Engl, H. P. Eichfeld, R. Hagelauer, and A. A. Abidi, "A 1.2 V 10-b 100-MSamples/s A/D converter in 0.12 μm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, June 2002, pp. 326-327.
3. 2 90nm CMOS pipeline ADC for flat-panel display applications," in Proc. Int. Solid-State Circuits Conf., Feb. 2007, pp. 458-459.
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5. G. Geelen and E. Paulus, "An 8b 600MS/S 200mW CMOS folding A/D converter using an amplifier preset technique," in Proc. Int. Solid-State Circuits Conf., Feb. 2004, pp. 254-526.
6. 2," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 18871895, Dec. 1997.