메뉴 건너뛰기




Volumn 33, Issue 12, 1998, Pages 1912-1919

An analog background calibration technique for time-interleaved analog-to-digital converters

Author keywords

Adaptive systems; Analog digital conversion; Calibration; CMOS analog integrated circuits

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CALIBRATION; CMOS INTEGRATED CIRCUITS; SIGNAL PROCESSING; SIGNAL TO NOISE RATIO;

EID: 0032308947     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.735531     Document Type: Article
Times cited : (125)

References (34)
  • 1
    • 0019265826 scopus 로고
    • Time interleaved converter arrays
    • Dec.
    • W. C. Black and D. A. Hodges, "Time interleaved converter arrays," IEEE J. Solid-State Circuits, vol. SC-15, pp. 1022-1029, Dec. 1980.
    • (1980) IEEE J. Solid-State Circuits , vol.SC-15 , pp. 1022-1029
    • Black, W.C.1    Hodges, D.A.2
  • 2
    • 0027576932 scopus 로고
    • An 8-b 85 MS/s Parallel pipelined A/D converter in 1-μm CMOS
    • Apr.
    • C. Conroy, D. Cline, and P. Gray, "An 8-b 85 MS/s Parallel pipelined A/D converter in 1-μm CMOS," IEEE J. Solid-State Circuits, vol. 28, pp. 447-454, Apr. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , pp. 447-454
    • Conroy, C.1    Cline, D.2    Gray, P.3
  • 4
    • 0024018237 scopus 로고
    • Digital spectra of nonuniformly sampled signals: Fundamentals and high-speed waveform digitizers
    • June
    • Y. C. Jenq, "Digital spectra of nonuniformly sampled signals: Fundamentals and high-speed waveform digitizers," IEEE Trans. Instrum. Meas., vol. 37, pp. 245-251, June 1988.
    • (1988) IEEE Trans. Instrum. Meas. , vol.37 , pp. 245-251
    • Jenq, Y.C.1
  • 5
    • 0025383716 scopus 로고
    • Digital spectra of nonuniformly sampled signals: A robust sampling time offset estimation algorithm for ultra high-speed waveform digitizers using interleaving
    • Feb.
    • _, "Digital spectra of nonuniformly sampled signals: A robust sampling time offset estimation algorithm for ultra high-speed waveform digitizers using interleaving," IEEE Trans, Instrum. Meas., vol. 39, pp 71-75, Feb. 1990.
    • (1990) IEEE Trans, Instrum. Meas. , vol.39 , pp. 71-75
  • 6
    • 0026240449 scopus 로고
    • Analysis of mismath effects among A/D converters in a time-interleaved waveform digitizer
    • Oct.
    • A. Petraglia and S. K. Mitra, "Analysis of mismath effects among A/D converters in a time-interleaved waveform digitizer," IEEE Trans. Instrum. Meas., vol. 40, pp. 831-835, Oct. 1991.
    • (1991) IEEE Trans. Instrum. Meas. , vol.40 , pp. 831-835
    • Petraglia, A.1    Mitra, S.K.2
  • 8
    • 0027553563 scopus 로고
    • A 10-b 50-MHz pipelined CMOS A/D converter with S/H
    • Mar.
    • M. Yotsuyanagi, T. Etoh, and K. Hirata, "A 10-b 50-MHz pipelined CMOS A/D converter with S/H," IEEE J. Solid-State Circuits, vol. 28, pp. 292-300, Mar. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , pp. 292-300
    • Yotsuyanagi, M.1    Etoh, T.2    Hirata, K.3
  • 10
    • 0029293925 scopus 로고
    • A 13-b 10-Msample/s ADC Digitally calibrated with oversampling delta-sigma converter
    • Apr.
    • T.-H. Shu, B. S. Song, and K. Bacrania, "A 13-b 10-Msample/s ADC Digitally calibrated with oversampling delta-sigma converter," IEEE J. Solid-State Cirucits, vol. 30, pp. 443-52, Apr. 1995.
    • (1995) IEEE J. Solid-State Cirucits , vol.30 , pp. 443-452
    • Shu, T.-H.1    Song, B.S.2    Bacrania, K.3
  • 12
    • 0031078998 scopus 로고    scopus 로고
    • Background digital calibration techniques for pipelined ADC's
    • Feb.
    • U. K. Moon and B. S. Song, "Background digital calibration techniques for pipelined ADC's," IEEE Trans. Circuits Syst, II, vol. 44, pp. 102-109, Feb. 1997.
    • (1997) IEEE Trans. Circuits Syst, II , vol.44 , pp. 102-109
    • Moon, U.K.1    Song, B.S.2
  • 13
    • 0031359733 scopus 로고    scopus 로고
    • A 15-b 5-Msamples/s low-spurious CMOS ADC
    • Dec.
    • S. U Kwak and B. S. Soog. "A 15-b 5-Msamples/s low-spurious CMOS ADC," IEEE J. Solid-State Cirucits, vol. 32, pp. 1866-1875, Dec. 1997.
    • (1997) IEEE J. Solid-State Cirucits , vol.32 , pp. 1866-1875
    • Kwak, S.U.1    Soog, B.S.2
  • 16
    • 0029266593 scopus 로고
    • Comparison of DC offset effects in four LMS adaptive algorithms
    • Mar.
    • A. Shoval, M. Snelgrove, and D. Johns, "Comparison of DC offset effects in four LMS adaptive algorithms," IEEE Trans. Circuits Syst. II, vol. 42, pp. 183, Mar. 1995
    • (1995) IEEE Trans. Circuits Syst. II , vol.42 , pp. 183
    • Shoval, A.1    Snelgrove, M.2    Johns, D.3
  • 17
    • 0003807773 scopus 로고
    • Englewood Cliffs, NJ: Prentice-Hall
    • S. Haykin, Adaptive Filter Theory. Englewood Cliffs, NJ: Prentice-Hall, 1986, pp. 681-690.
    • (1986) Adaptive Filter Theory , pp. 681-690
    • Haykin, S.1
  • 18
    • 0031655847 scopus 로고    scopus 로고
    • Digital background calibration of a 10-b 4O-MS/s parallel pipelined ADC
    • Feb.
    • D. Fu, K. Dyer, S. Lewis, and P. Hurst, "Digital background calibration of a 10-b 4O-MS/s parallel pipelined ADC," in Proc. IEEE ISSCC, Feb. 1998, pp. 140-142.
    • (1998) Proc. IEEE ISSCC , pp. 140-142
    • Fu, D.1    Dyer, K.2    Lewis, S.3    Hurst, P.4
  • 19
    • 0027810812 scopus 로고
    • Adaptive switched-capacitor filters based on the LMS algorithm
    • Dec
    • U. Menzi and G. Moschytz, "Adaptive switched-capacitor filters based on the LMS algorithm," IEEE Trans. Circuits Syst I, vol. 40, pp. 929-942, Dec 1993.
    • (1993) IEEE Trans. Circuits Syst I , vol.40 , pp. 929-942
    • Menzi, U.1    Moschytz, G.2
  • 22
    • 0030244314 scopus 로고    scopus 로고
    • A 35 Mb/s mixed-signal decisionfeedback equalizer for disk drives in 2-μm CMOS
    • Sept.
    • J. Brown, P. Hurst, and L. Der, "A 35 Mb/s mixed-signal decisionfeedback equalizer for disk drives in 2-μm CMOS," IEEE J. Solid-State Circuits, vol. 31, pp. 1258-1266, Sept. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , pp. 1258-1266
    • Brown, J.1    Hurst, P.2    Der, L.3
  • 23
    • 0024737353 scopus 로고
    • A parasitic-insensitive area-efficient approach to realizing very large time constants in switched-capacitor circuits
    • Sept.
    • K. Nagaraj, "A parasitic-insensitive area-efficient approach to realizing very large time constants in switched-capacitor circuits," IEEE Trans. Circuits Syst., vol. 36, pp. 1210-1216, Sept. 1989.
    • (1989) IEEE Trans. Circuits Syst. , vol.36 , pp. 1210-1216
    • Nagaraj, K.1
  • 24
    • 84944022420 scopus 로고
    • Are-efficient gain-and offset-compensated very-large-time-constant SC biquads
    • May
    • W. H. Ki and G. C. Temes, "Are-efficient gain-and offset-compensated very-large-time-constant SC biquads," ISCAS, vol. 3, pp. 1187-1190, May 1992.
    • (1992) ISCAS , vol.3 , pp. 1187-1190
    • Ki, W.H.1    Temes, G.C.2
  • 26
    • 0011179372 scopus 로고
    • Basic MOS operational amplifier design - An overview
    • P. Gray, D. Hodges, and R. Brodersen, Eds. New York: IEEE Press, Wiley
    • P. Gray, "Basic MOS operational amplifier design - An overview," Analog MOS Integrated Circuits, P. Gray, D. Hodges, and R. Brodersen, Eds. New York: IEEE Press, Wiley, 1980, pp. 28-49.
    • (1980) Analog MOS Integrated Circuits , pp. 28-49
    • Gray, P.1
  • 29
    • 0021385908 scopus 로고
    • Resolution below the least significant bit in digital systems with dither
    • Mar.
    • J. Vederkooy and S. Lipshitz, "Resolution below the least significant bit in digital systems with dither," J. Audio Eng. Soc., vol. 32, no. 3, pp. 106-112, Mar. 1984.
    • (1984) J. Audio Eng. Soc. , vol.32 , Issue.3 , pp. 106-112
    • Vederkooy, J.1    Lipshitz, S.2
  • 30
    • 0028422448 scopus 로고
    • Linearizing average transfer characteristics of ideal ADC's via analog and digital dither
    • Apr.
    • M. Wagdy and M. Goff, "Linearizing average transfer characteristics of ideal ADC's via analog and digital dither," IEEE Trans. Instrum. Meas., vol. 43, p. 147, Apr. 1994.
    • (1994) IEEE Trans. Instrum. Meas. , vol.43 , pp. 147
    • Wagdy, M.1    Goff, M.2
  • 31
    • 0021445655 scopus 로고
    • The design of high-performance anlog circuits on digital CMOS chips
    • June
    • E. Vittoz, "The design of high-performance anlog circuits on digital CMOS chips," IEEE J. Solid-State Circuits, vol. SC-20, pp. 657-665, June 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SC-20 , pp. 657-665
    • Vittoz, E.1
  • 34
    • 0029269932 scopus 로고
    • A 10 b, 20 Msample/s, 35 mW pipeline A/D converter
    • Mar.
    • T. Cho and P. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , pp. 166-172
    • Cho, T.1    Gray, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.