A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 12, 2003, Pages 2031-2039

  Min, Byung Moo ^a   Kim, Peter ^a   Bowman III, Frederick W ^b   Boisvert, David M ^a   Aude, Arlo J ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^b NONE

Author keywords

Analog to digital conversion; Early comparison scheme with constant delay circuit; Low power pipelined analog to digital conversion; Opamp sharing technique

Indexed keywords

AMPLIFICATION; AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; BANDWIDTH; CAPACITANCE; CAPACITORS; COMPARATOR CIRCUITS; DATA COMMUNICATION SYSTEMS; DEGRADATION; FEEDBACK; MOS DEVICES; OPTICAL RESOLVING POWER; SIGNAL TO NOISE RATIO; TRANSCONDUCTANCE;

CONSTANT DELAY CIRCUITS; GAIN MISMATCH; OPAMP SHARING TECHNIQUE; POWER CONSUMPTION;

CMOS INTEGRATED CIRCUITS;

EID: 0346972345     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.819166     Document Type: Conference Paper

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