A 2.2mW 5b 1.75GS/S folding flash ADC in 90nm digital CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 251-253

  Verbruggen, Bob ^a,b   Craninckx, Jan ^a   Kuijk, Maarten ^b   Wambacq, Piet ^a,b   Van Der Plas, Geert ^a  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORKS (CIRCUITS); SOLID STATE DEVICES;

DIGITAL CMOS; FLASH-ADC; FOLDING TECHNIQUE; NYQUIST FREQUENCY;

CMOS INTEGRATED CIRCUITS;

EID: 49549089559     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523152     Document Type: Conference Paper

References (5)

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2. G. Geelen and E. Paulus, "An 8b 600MS/s 200mW CMOS Folding A/D Converter Using an Amplifier Preset Technique," ISSCC Digest of Technical Papers, pp. 254-255, Feb. 2004.
3. S. Limotyrakis, S. D. Kulchycki, D. K. Su and B. A. Wooley, "A 150MS/s 8b 71-mW CMOS Time-Interleaved ADC," IEEE J. Solid State Circuits, vol. 40, no. 5, pp. 1057-1067, May 2005.
4. P. Xiao, K. Jenkins, M. Soyuer, et al., "A 4b 8GSample/s A/D Converter in SiGe Bipolar Technology," ISSCC Dig. Tech. Papers, pp. 124-125, Feb. 1997.
5. G. Van der Plas, S. Decoutere and S. Donnay, "A 0.16pJ/Conversion- Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process," ISSCC Dig. Tech. Papers, pp. 566-567, Feb. 2006.